DF36054FPJV Renesas Electronics America, DF36054FPJV Datasheet - Page 216

• Manufacturer Part Number: DF36054FPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054FPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Timer Z
[Legend]
X: Don't care
12.3.11 Timer Status Register (TSR)
TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture
of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a
corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers,
one for each channel.
Rev. 4.00 Mar. 15, 2006 Page 182 of 556
REJ09B0026-0400
Bit
2
1
0
Bit
7, 6
5
4
Bit Name
IOC2
IOC1
IOC0
Bit Name
UDF*
OVF
Initial
value
0
0
0
Initial
Value
All 1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I/O Control C2 to C0
GRC is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRC compare match
010: 1 output by GRC compare match
011: Toggle Output by GRC compare match
GRC is an input capture register:
100: Input capture to GRC at the rising edge
101: Input capture to GRC at the falling edge
11X: Input capture to GRC at both rising and falling edges
Description
Reserved
These bits are always read as 1.
Underflow Flag
[Setting condition]
[Clearing condition]
Overflow Flag
[Setting condition]
[Clearing condition]
When TCNT_1 underflows
When 0 is written to UDF after reading UDF = 1
When the TCNT value underflows
When 0 is written to OVF after reading OVF = 1