HD6417020SVX12IV Renesas Electronics America, HD6417020SVX12IV Datasheet - Page 385
HD6417020SVX12IV
Manufacturer Part Number
HD6417020SVX12IV
Description
MCU 3/5V 0K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12IV
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
Transmitting and Receiving Data (SCI initialization (asynchronous mode)): Before
transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register
(SCR), then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCI operation becomes unreliable if the clock is stopped.
Figure 13.4 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is
as follows:
1. Select the communication format in the serial mode register (SMR).
2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external
3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE
4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the
RENESAS 368
Figure 13.3 Phase Relationship Between Output Clock and Serial Data (asynchronous
clock is used.
and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts
immediately after the setting is made to SCR.
serial control register (SCR) to 1. Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE
or RE enables the SCI to use the TxD or RxD pin. The initial states are the mark transmit state,
and the idle receive state (waiting for a start bit).
0
D0
D1
D2
D3
1 frame
D4
D5
mode)
D6
D7
0/1
1
1
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