HD6417020SVX12IV Renesas Electronics America, HD6417020SVX12IV Datasheet - Page 185
HD6417020SVX12IV
Manufacturer Part Number
HD6417020SVX12IV
Description
MCU 3/5V 0K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12IV
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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BREQ is sampled one state before the bus cycle. If BREQ is input without satisfying tBRQS, the
bus is released after executing cycle B following the end of bus cycle A, as shown in figure 8.43.
The maximum number of states from BREQ input to bus release are used when B is a cycle
comprising the maximum number of states for which the bus is not released; the number of states
is the maximum number of states for which bus is not released + approx. 4.5 states.
The maximum number of states for which the bus is not released requires careful investigation.
1. Cycles in which bus is not released
(a) One bus cycle
(b) TAS instruction read cycle and write cycle
The bus is never released during one bus cycle. For example, in the case of a longword
read (or write) in 8-bit ordinary space, one bus cycle consists of 4 memory accesses to 8-bit
ordinary space, as shown in figure 8.44. The bus is not released between these accesses.
Assuming one memory access to require 2 states, the bus is not released for a period of 8
states.
The bus is never released during a TAS instruction read cycle and write cycle (figure 8.45).
The TAS instruction read cycle and write cycle should be regarded as one bus cycle during
which the bus is not released.
Bus cycle
Figure 8.43 When BREQ is Input without Satisfying tBRQS
BREQ
BACK
tBRQS
CK
A
Figure 8.44 One Bus Cycle
8 bits 8 bits
Cycle during which
bus is not released
B
8 bits 8 bits
tBACD1
Bus release
RENESAS 165
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