HD6417020SVX12IV Renesas Electronics America, HD6417020SVX12IV Datasheet - Page 383
HD6417020SVX12IV
Manufacturer Part Number
HD6417020SVX12IV
Description
MCU 3/5V 0K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12IV
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Quantity
Price
Company:
Part Number:
HD6417020SVX12IV
Manufacturer:
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Quantity:
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HD6417020SVX12IV
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Renesas Electronics America
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13.3.2
Operation in Asynchronous Mode
In the asynchronous mode, each transmitted or received character begins with a start bit and ends
with a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication, the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start
bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit
rate. Receive data is latched at the center of each bit.
Idling (mark state)
1
(LSB)
(MSB)
1
Serial
0
D
D
D
D
D
D
D
D
0/1
1
1
0
1
2
3
4
5
6
7
data
Start
Parity
Stop
bit
bit
bit
Transmit/receive data
7 or 8 bits
1 bit
1 or
1 or
no bit
2 bits
One unit of communication (characters or frames)
Figure 13.2 Data Format in Asynchronous Communication (Example: 8-bit data with
parity and two stop bits)
RENESAS 366
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