HD6417020SVX12IV Renesas Electronics America, HD6417020SVX12IV Datasheet - Page 348

MCU 3/5V 0K PB-FREE 100-TQFP

HD6417020SVX12IV

Manufacturer Part Number
HD6417020SVX12IV
Description
MCU 3/5V 0K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6417020SVX12IV

Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
HD6417020SVX12IV
Manufacturer:
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Quantity:
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Part Number:
HD6417020SVX12IV
Manufacturer:
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Quantity:
10 000
12.2.2
The timer control/status register (TCSR) is an eight-bit readable and writable register. The TCSR
differs from other registers in being more difficult to write. See section 12.2.4, Register Access,
for details. Its functions include selecting the timer mode and clock source. Bits 7–5 are initialized
to 000 by a reset or in standby mode. Bits 2–0 are initialized to 000 by a reset, but retain their
values in the standby mode.
• Bit 7 (overflow flag (OVF)): OVF indicates that the TCNT has overflowed from H'FF–H'00. It
Bit 7: OVF
0
1
• Bit 6 (timer mode select (WT/IT)): WT/IT selects whether to use the WDT as a watchdog
Bit 6: WT/IT
0
1
• Bit 5 (timer enable (TME)): TME enables or disables the timer.
RENESAS 330
is not set in the watchdog timer mode.
timer or interval timer. When the TCNT overflows, the WDT either generates an interval timer
interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected.
Initial value:
Initial value:
Bit name:
Bit name:
Timer Control/Status Register (TCSR)
R/W:
R/W:
Bit:
Bit:
R/(W)*
OVF
R/W
7
0
7
0
Description
No overflow of TCNT in interval timer mode (initial value)
Cleared by reading OVF, then writing 0 in OVF
TCNT overflow in the interval timer mode
Description
Interval timer mode: interval timer interrupt to the CPU when TCNT
overflows (initial value)
Watchdog timer mode: WDTOVF signal output externally when TCNT
overflows. Section 12.2.3, Reset Control/Status Register (RSTCSR),
describes in detail what happens when TCNT overflows in the
watchdog timer mode.
WT/IT
R/W
R/W
6
0
6
0
TME
R/W
R/W
5
0
5
0
R/W
4
0
4
1
R/W
3
0
3
1
CKS2
R/W
R/W
2
0
2
0
CKS1
R/W
R/W
1
0
1
0
CKS0
R/W
R/W
0
0
0
0

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