HD64F3664BPV Renesas Electronics America, HD64F3664BPV Datasheet - Page 11

• Manufacturer Part Number: HD64F3664BPV
• Description: MCU 3/5V 32K,PB-FREE 42-DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664BPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Section 2 CPU......................................................................................................13
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Section 3 Exception Handling .............................................................................51
3.1
3.2
Features................................................................................................................................. 1
Internal Block Diagram......................................................................................................... 3
Pin Arrangement ................................................................................................................... 5
Pin Functions ........................................................................................................................ 9
Address Space and Memory Map ....................................................................................... 14
Register Configuration........................................................................................................ 17
2.2.1
2.2.2
2.2.3
Data Formats....................................................................................................................... 21
2.3.1
2.3.2
Instruction Set ..................................................................................................................... 24
2.4.1
2.4.2
Addressing Modes and Effective Address Calculation....................................................... 35
2.5.1
2.5.2
Basic Bus Cycle .................................................................................................................. 41
2.6.1
2.6.2
CPU States .......................................................................................................................... 43
Usage Notes ........................................................................................................................ 44
2.8.1
2.8.2
2.8.3
Exception Sources and Vector Address .............................................................................. 51
Register Descriptions.......................................................................................................... 53
3.2.1
3.2.2
3.2.3
General Registers................................................................................................ 18
Program Counter (PC) ........................................................................................ 19
Condition-Code Register (CCR)......................................................................... 19
General Register Data Formats ........................................................................... 21
Memory Data Formats ........................................................................................ 23
Table of Instructions Classified by Function ...................................................... 24
Basic Instruction Formats ................................................................................... 34
Addressing Modes .............................................................................................. 35
Effective Address Calculation ............................................................................ 39
Access to On-Chip Memory (RAM, ROM)........................................................ 41
On-Chip Peripheral Modules .............................................................................. 42
Notes on Data Access to Empty Areas ............................................................... 44
EEPMOV Instruction.......................................................................................... 44
Bit Manipulation Instruction............................................................................... 45
Interrupt Edge Select Register 1 (IEGR1) .......................................................... 53
Interrupt Edge Select Register 2 (IEGR2) .......................................................... 54
Interrupt Enable Register 1 (IENR1) .................................................................. 55
Contents
Rev. 6.00 Mar. 24, 2006 Page ix of xxviii