HD64F3664BPV Renesas Electronics America, HD64F3664BPV Datasheet - Page 391
HD64F3664BPV
Manufacturer Part Number
HD64F3664BPV
Description
MCU 3/5V 32K,PB-FREE 42-DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.US3664-BAG1.pdf
(446 pages)
Specifications of HD64F3664BPV
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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8. Block transfer instructions
Notes: 1. The number of states in cases where the instruction code and its operands are located
EEPMOV
EEPMOV. B
EEPMOV. W
2. n is the value set in register R4L or R4.
in on-chip memory is shown here. For other cases see appendix A.3, Number of
Execution States.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Mnemonic
synchronization with the E clock is variable.
—
—
Instruction Length (bytes)
Addressing Mode and
4
4
if R4L
until
else next
if R4
until
else next
repeat @R5
repeat @R5
0 then
Operation
0 then
Rev. 6.00 Mar. 24, 2006 Page 361 of 412
R5+1
R6+1
R4L–1
R4L=0
R5+1
R6+1
R4–1
R4=0
@R6
@R6
R4
R5
R6
R5
R6
R4L
—
—
I
Condition Code
—
—
H
—
—
N
REJ09B0142-0600
—
—
Z
—
—
V
—
— 8+
C
Appendix
4n
4n
States
8+
No. of
*2
*2
*1
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