D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 755

MCU 3V 0K 100-TQFP

D12312SVTE25

Manufacturer Part Number
D12312SVTE25
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12312SVTE25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTE25
HD6412312SVTE25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12312SVTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
SCI Interface Setting by Host: When boot mode is initiated, this LSI measures the low period of
asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host.
The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates
the bit rate of transmission by the host by means of the measured low period and transmits the bit
adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment
end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When
reception is not executed normally, boot mode is initiated again (reset) and the operation described
above must be executed. The bit rate between the host and this LSI is not matched by the bit rate
of transmission by the host and system clock frequency of this LSI. To operate the SCI normally,
the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps.
The system clock frequency which can automatically adjust the transfer bit rate of the host and the
bit rate of this LSI is shown in table 17.53. Boot mode must be initiated in the range of this system
clock.
tool and program
programming
Boot
Host
data
Start
bit
Figure 17.66 Automatic Adjustment Operation of SCI Bit Rate
Figure 17.65 System Configuration in Boot Mode
D0
Measure low period (9 bits) (data is H'00)
Control command, program data
D1
Reply response
D2
D3
D4
Rev.7.00 Feb. 14, 2007 page 721 of 1108
analysis execution
Control command,
software (on-chip)
RxD1
TxD1
D5
On-chip SCI1
D6
This LSI
D7
On-chip RAM
Stop bit
High period of
at least 1 bit
memory
REJ09B0089-0700
Flash
Section 17 ROM

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