DF2212CUNP24V Renesas Electronics America, DF2212CUNP24V Datasheet - Page 325

MCU 16BIT FLASH 3V 128K 64-QFN

DF2212CUNP24V

Manufacturer Part Number
DF2212CUNP24V
Description
MCU 16BIT FLASH 3V 128K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of DF2212CUNP24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2212CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
8.12.2
PGDR stores output data for the port G pins.
Notes: 1. Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read.
8.12.3
PORTG indicates the pin states of the port G.
Notes: 1. Determined by the states of pins PG4 to PG0.
Bit
7 to
5
4
3
2
1
0
Bit
7 to
5
4
3
2
1
0
Bit Name Initial Value
Bit Name Initial Value
PG4DR*
PG3DR*
PG2DR*
PG1DR
PG0DR*
PG4*
PG3*
PG2*
PG1
PG0*
2. Reserved in the H8S/2218 Group. If this bit is read, an undefined value will be read.
2. Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read.
3. Reserved in the H8S/2218 Group. If this bit is read, an undefined value will be read.
Port G Data Register (PGDR)
Port G Register (PORTG)
This bit cannot be modified.
This bit cannot be modified.
2
2
2
3
1
1
1
2
Undefined
0
0
0
0
0
Undefined
⎯*
⎯*
⎯*
⎯*
⎯*
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
Reserved
These bits are undefined and cannot be modified.
Store output data for a pin that functions as a general
output port.
Reserved
These bits are undefined.
If the port G is read while PGDDR bits are set to 1, the
PGDR value is read. If the port G is read while PGDDR
bits are cleared to 0, the pin states are read.
Description
Description
Rev.7.00 Dec. 24, 2008 Page 269 of 698
REJ09B0074-0700

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