MC68HC705C8AFNE Freescale Semiconductor, MC68HC705C8AFNE Datasheet - Page 86

• Manufacturer Part Number: MC68HC705C8AFNE
• Description: IC MCU 8BIT 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8AFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Parallel Input/Output (I/O)
7.5.2 Data Direction Register C
Technical Data
86
NOTE:
Address:
The contents of data direction register C (DDRC) shown in
determine whether each port C pin is an input or an output. Writing a
logic 1 to a DDRC bit enables the output buffer for the associated port C
pin; a logic 0 disables the output buffer. A reset clears all DDRC bits,
configuring all port C pins as inputs.
DDRC7–DDRC0 — Port C Data Direction Bits
Avoid glitches on port C pins by writing to the port C data register before
changing DDRC bits from logic 0 to logic 1.
Reset:
Read:
Write:
These read/write bits control port C data direction. Reset clears bits
DDRC7–DDRC0.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
DDRC7
$0006
Bit 7
0
Figure 7-8. Data Direction Register C (DDRC)
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Parallel Input/Output (I/O)
DDRC6
6
0
DDRC5
5
0
DDRC4
4
0
DDRC3
3
0
DDRC2
MC68HC705C8A — Rev. 3
2
0
DDRC1
1
0
Figure 7-8
DDRC0
Bit 0
0