MC68HC705C8AFNE Freescale Semiconductor, MC68HC705C8AFNE Datasheet - Page 146

IC MCU 8BIT 44-PLCC

MC68HC705C8AFNE

Manufacturer Part Number
MC68HC705C8AFNE
Description
IC MCU 8BIT 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705C8AFNE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
304 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Processor Series
HC705C
Core
HC05
Data Bus Width
8 bit
Data Ram Size
304 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
24
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705C8AFNE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Serial Peripheral Interface (SPI)
11.6 Serial Clock Polarity and Phase
Technical Data
146
CPHA
0
1
0
1
CPOL
0
0
1
1
CAPTURE STROBE
SDO/SDI
SCK (A)
SCK (B)
SCK (C)
SCK (D)
SS
To accommodate the different serial communication requirements of
peripheral devices, software can change the phase and polarity of the
SPI serial clock. The clock polarity bit (CPOL) and the clock phase bit
(CPHA), both in the SPCR, control the timing relationship between the
serial clock and the transmitted data.
and CPHA bits affect the clock/data timing.
Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram
MSB
Freescale Semiconductor, Inc.
MASTER/SLAVE
For More Information On This Product,
Figure 11-6. SPI Clock/Data Timing
PD2/MISO
PD3/MOSI
MCU 1
PORT
PD4/SCK
I/O
PD5/SS
BIT 6
Serial Peripheral Interface (SPI)
0
1
2
3
Go to: www.freescale.com
BIT 5
SLAVE MCU 2
BIT 4
SLAVE MCU 1
BIT 3
Figure 11-6
BIT 2
SLAVE MCU 0
BIT 1
MC68HC705C8A — Rev. 3
shows how the CPOL
LSB
MASTER/SLAVE
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
0
1
2
3
MCU 2
PORT
I/O

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