MC9S12XEQ384CAL Freescale Semiconductor, MC9S12XEQ384CAL Datasheet - Page 72
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MC9S12XEQ384CAL
Manufacturer Part Number
MC9S12XEQ384CAL
Description
MCU 16BIT 384K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEQ384CAL
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
24 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 1 Device Overview MC9S12XE-Family
1.2.3.76
PS0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 0 (SCI0).
1.2.3.77
PT[7:6] are general-purpose input or output pins. They can be configured as input capture or output
compare pins IOC[7:6] of the enhanced capture timer (ECT).
1.2.3.78
PT[5] is a general-purpose input or output pin. It can be configured as input capture or output compare pin
IOC[5] of the enhanced capture timer (ECT) or can be configured to output the VREG_API signal.
1.2.3.79
PT[4:0] are general-purpose input or output pins. They can be configured as input capture or output
compare pins IOC[4:0] of the enhanced capture timer (ECT).
1.2.4
MC9S12XE-Family power and ground pins are described below.
Because fast signal transitions place high, short-duration current demands on the power supply, use bypass
capacitors with high-frequency characteristics and place them as close to the MCU as possible.
1.2.4.1
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are
loaded. All V
1.2.4.2
Input to the internal voltage regulator. The internal voltage regulator is turned off, if V
1.2.4.3
Power is supplied to the MCU core from the internal voltage regulator, whose load capacitor must be
connected to VDD. The voltage supply of nominally 1.8V is derived from the internal voltage regulator.
The return current path is through the VSS1,VSS2 and VSS3 pins. No static external loading of these pins
is permitted.
72
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Power Supply Pins
PS0 / RXD0 — Port S I/O Pin 0
PT[7:6] / IOC[7:6] — Port T I/O Pins [7:6]
PT[5] / IOC[5] / VREG_API— Port T I/O Pins [5]
PT[4:0] / IOC[4:0] — Port T I/O Pins [4:0]
VDDX[7:1], VSSX[7:1] — Power and Ground Pins for I/O Drivers
DDX
VDDR — Power Pin for Internal Voltage Regulator
VDD, VSS1,VSS2,VSS3 — Core Power Pins
All V
pins are connected together internally. All V
SS
pins must be connected together in the application.
MC9S12XE-Family Reference Manual , Rev. 1.23
NOTE
SSX
pins are connected together internally.
Freescale Semiconductor
DDR
is tied to ground
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