MC9S12XEQ384CAL Freescale Semiconductor, MC9S12XEQ384CAL Datasheet - Page 641
MC9S12XEQ384CAL
Manufacturer Part Number
MC9S12XEQ384CAL
Description
MCU 16BIT 384K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEQ384CAL
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
24 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
1. Read: Anytime when TXEx flag is set (see
16.3.3.5
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see
“MSCAN Control Register 0
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
1. Read: Anytime when TXEx flag is set (see
Freescale Semiconductor
Module Base + 0x00XD
Module Base + 0x00XE
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Write: Anytime when TXEx flag is set (see
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Write: Unimplemented
•
Reset:
Reset:
The transmission buffer with the lowest local priority field wins the prioritization.
W
W
R
R
Time Stamp Register (TSRH–TSRL)
TSR15
PRIO7
0
7
7
x
Figure 16-37. Time Stamp Register — High Byte (TSRH)
Figure 16-36. Transmit Buffer Priority Register (TBPR)
TSR14
PRIO6
6
0
6
x
(CANCTL0)”). In case of a transmission, the CPU can only read the time
MC9S12XE-Family Reference Manual Rev. 1.23
Section 16.3.2.7, “MSCAN Transmitter Flag Register
Section 16.3.2.7, “MSCAN Transmitter Flag Register
Section 16.3.2.7, “MSCAN Transmitter Flag Register
TSR13
PRIO5
0
5
5
x
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
TSR12
PRIO4
4
0
4
x
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
TSR11
PRIO3
0
x
3
3
TSR10
PRIO2
2
0
2
x
(CANTFLG)”) and the
(CANTFLG)”) and the
(CANTFLG)”) and the
Access: User read/write
Access: User read/write
PRIO1
TSR9
Section 16.3.2.1,
0
x
1
1
PRIO0
TSR8
0
0
0
x
641
(1)
(1)
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