MC908MR8MPE Freescale Semiconductor, MC908MR8MPE Datasheet - Page 228

• Manufacturer Part Number: MC908MR8MPE
• Description: IC MCU 8BIT 8K FLASH 28-PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR8MPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Timer Interface B (TIMB)
12.4.1 TIMB Counter Prescaler
12.4.2 Input Capture
Technical Data
228
The two TIMB channels are programmable independently as input
capture or output compare channels.
The TIMB clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIMB status and control register
select the TIMB clock source.
An input capture function has three basic parts:
Two 8-bit registers, which make up the 16-bit input capture register, are
used to latch the value of the free-running counter after the
corresponding input capture edge detector senses a defined transition.
The polarity of the active edge is programmable. The level transition
which triggers the counter transfer is defined by the corresponding input
edge bits (ELSxB and ELSxA in TBSC0 through TBSC1 control registers
with x referring to the active channel number). When an active edge
occurs on the pin of an input capture channel, the TIMB latches the
contents of the TIMB counter into the TIMB channel registers,
TCHxH–TCHxL. Input captures can generate TIMB CPU interrupt
requests. Software can determine that an input capture event has
occurred by enabling input capture interrupts or by polling the status flag
bit.
The free-running counter contents are transferred to the TIMB channel
status and control register, TBCHxH–TBCHxL, (see
Channel
whether the TIMB channel flag (CH0F–CH1F in TBSC0–TBSC1
registers) is set or clear. When the status flag is set, a CPU interrupt is
generated if enabled. The value of the count latched or “captured” is the
time of the event. Because this value is stored in the input capture
register two bus cycles after the actual event occurs, user software can
•
•
•
Edge select logic
Input capture latch
16-bit counter
Registers) on each proper signal transition regardless of
Timer Interface B (TIMB)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
12.10.5 TIMB