MC908MR8MPE Freescale Semiconductor, MC908MR8MPE Datasheet - Page 132

• Manufacturer Part Number: MC908MR8MPE
• Description: IC MCU 8BIT 8K FLASH 28-PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR8MPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Clock Generator Module (CGM)
8.7 Interrupts
Technical Data
132
NOTE:
VRS[7:4] — VCO Range Select Bits
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming may result in failure of the PLL to achieve lock.
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as
logic 0.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
f
8.6.1 PLL Control
PLLON bit in the PLL control register (PCTL) is set. See
Special Programming
select bits disables the PLL and clears the BCS bit in the PCTL. See
8.4.3 Base Clock Selector Circuit
Programming Exceptions
Reset initializes the bits to $6 to give a default range multiply
value of 6.
VRS
. See
Clock Generator Module (CGM)
8.4.2.1 PLL
Register. VRS[7:4] cannot be written when the
Circuits,
Exceptions. A value of $0 in the VCO range
for more information.
8.4.2.4 Programming the
and
8.4.2.5 Special
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
8.4.2.5
PLL, and