M38503G4AFP#U1 Renesas Electronics America, M38503G4AFP#U1 Datasheet - Page 56

• Manufacturer Part Number: M38503G4AFP#U1
• Description: IC 740/3850 MCU QZ-ROM 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38503G4AFP#U1

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: QzROM
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3850 Group (Spec.A QzROM version)
Rev.2.13
REJ03B0125-0213
2. Notes when selecting clock asynchronous serial I/O
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to
“0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S
I/O ports, the transmission data is not output). When data is
written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O1
enable bit is set to “1” at this time, the data during internally
shifting is output to the TxD pin and an operation failure occurs.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to
“0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S
I/O ports, the transmission data is not output). When data is
written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O1
enable bit is set to “1” at this time, the data during internally
shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
3. Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission
and the reception circuits are reset by clearing both the transmit
enable bit and the receive enable bit to “0”.
Fig 54. Sequence of setting serial I/O1 control register
4. Data transmission control with referring to transmit
The transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after writing
the data to the transmit buffer register, note the delay.
(Serial I/O1)
shift register completion flag (Serial I/O1)
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the serial I/O1
control register
Set both the transmit enable bit (TE) and the
receive enable bit (RE), or one of them to “1”
again
Apr 17, 2009
Page 54 of 56
CLK1
CLK1
, and S
, and S
Can be set with the
LDM instruction at
the same time
RDY1
RDY1
function as
function as
5. Transmit interrupt request when transmit enable bit
When the transmit interrupt is used, set the transmit interrupt
enable bit to transmit enabled as shown in the following
sequence.
(1) Set the interrupt enable bit to “0” (disabled) with CLB
(2) Prepare serial I/O for transmission/reception.
(3) Set the interrupt request bit to “0” with CLB instruction
(4) Set the interrupt enable bit to “1” (enabled).
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer
empty flag and transmit shift register completion flag are set to
“1”.
The interrupt request is generated and the transmission interrupt
request bit is set regardless of which of the two timings listed
below is selected as the timing for the transmission interrupt to
be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
6. Transmission control when external clock is
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the
S
buffer register (serial I/O shift register) at “H” of the S
level.
7. Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external
clock as synchronous clock, write the transmit data to the serial
I/O2 register (serial I/O shift register) at “H” of the transfer clock
input level.
Notes on PWM
The PWM starts after the PWM enable bit is set to enable and
“L” level is output from the PWM pin.
The length of this “L” level output is as follows:
CLK1
2
is set (Serial I/O1)
selected (Serial I/O1 clock synchronous mode)
×
instruction.
after 1 or more instruction has been executed.
f(X
n + 1
n + 1
f(X
input level. Also, write the transmit data to the transmit
IN
IN
)
)
(s)
(s)
(Count source selection bit = “0”,
where n is the value set in the prescaler)
(Count source selection bit = “1”,
where n is the value set in the prescaler)
CLK1
input