M38503G4AFP#U1 Renesas Electronics America, M38503G4AFP#U1 Datasheet - Page 26

• Manufacturer Part Number: M38503G4AFP#U1
• Description: IC 740/3850 MCU QZ-ROM 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38503G4AFP#U1

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: QzROM
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3850 Group (Spec.A QzROM version)
Rev.2.13
REJ03B0125-0213
SERIAL INTERFACE
• Serial I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O1. A dedicated timer is also
provided for baud rate generation.
Fig 20. Block diagram of clock synchronous serial I/O1
Fig 21. Operation of clock synchronous serial I/O1 function
buffer register (address 0018
Write pulse to receive/transmit
P2
P2
Receive enable signal S
P2
P2
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
7
6
/S
/S
4
5
/R
/T
RDY1
CLK1
X
X
X
D
IN
D
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
(TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
continuously from the T
Apr 17, 2009
Serial output T
Serial input R
F/F
BRG count source selection bit
RDY1
X
X
16
D
D
)
1/4
TBE = 0
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X
Falling-edge detector
D pin.
TBE = 1
TSC = 0
Receive buffer register
Receive shift register
D
D
Serial I/O1 synchronous clock selection bit
Data bus
0
0
Transmit buffer register
Transmit shift register
Data bus
Address 0018
Shift clock
D
D
Frequency division ratio 1/(n+1)
1
1
Baud rate generator
Shift clock
Address 0018
D
D
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
16
2
2
Address 001C
16
Clock control circuit
Clock control circuit
D
D
3
3
Serial I/O1 control register
Transmit interrupt source selection bit
Receive buffer full flag (RBF)
Serial I/O1 status register
16
1/4
D
D
4
4
16
) to “1”.
Receive interrupt request (RI)
Transmit buffer empty flag (TBE)
D
D
5
5
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
D
D
Address 0019
Address 001A
6
6
Overrun error (OE)
detection
RBF = 1
TSC = 1
D
D
7
7
16
16