R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 270

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Table 5.2.1 Interrupt Priority Levels
Chapter 5
5.2.3 ILVL2 to ILVL0 bis, IPL
ILVL2–ILVL0
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 5.2.1 shows how interrupt priority levels are set. Table 5.2.2 shows interrupt enable levels in
relation to IPL.
The following lists the conditions under which an interrupt request is acknowledged:
• I flag
• IR bit
• Interrupt priority level
The I flag, bits ILVL2 to ILVL0, and IPL are independent of each other, and they do not affect each other.
When the IPL or the interrupt priority level of an interrupt is changed, the altered level is reflected in
interrupt handling with the following timing:
• If the IPL is changed by an REIT instruction, the new level takes effect beginning with the instruction
• If the IPL is changed by a POPC, LDC, or LDIPL instruction, the new level takes effect beginning with
• If the interrupt priority level of a particular interrupt is changed by an instruction such as MOV, the
new level takes effect beginning with the instruction that is executed two or three clock cycles after the
that is executed two clock cycles after the last clock cycle of the REIT instruction.
the instruction that is executed three clock cycles after the last clock cycle of the instruction used.
last clock cycle of the instruction used.
101
000
001
010
011
100
110
111
2
2
2
2
2
2
2
2
Interrupts
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
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Interrupt Priority
Level
= 1
= 1
> IPL
Priority
High
Low
Table 5.2.2 Interrupt Priority Levels Enabled by IPL
010
101
110
111
000
001
011
100
IPL
2
2
2
2
2
2
2
2
Interrupt levels 5 and above are enabled.
Interrupt levels 1 and above are enabled.
Interrupt levels 2 and above are enabled.
Interrupt levels 3 and above are enabled.
Interrupt levels 4 and above are enabled.
Interrupt levels 6 and above are enabled.
Interrupt levels 7 and above are enabled.
All maskable interrupts are disabled.
Enabled interrupt priority
levels
5.2 Interrupt Control