R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 157

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Chapter 4 Instruction Codes
(1) Mnemonic
(2) Syntax
(3) Instruction code
(4) Table of cycles
Shows the mnemonic explained in the page.
Shows an instruction syntax using symbols.
Shows instruction code. Portions in parentheses ( ) may be omitted depending on the selected src/dest.
Contents at addresses following (start address of instruction + 2) are arranged as follows:
Shows the number of cycles required to execute the instruction and the number of bytes in the instruction.
The number of cycles may increase due to software wait states, etc.
The number of bytes in the instruction is indicated on the left side of the slash and the number of
execution cycles is indicated on the right side.
Correspondence
b7
.size
.W
0 1 1 1 0 1 0 SIZE 1 1 0 0
Content at start address
.B
SIZE
of instruction
0
1
page 137 of 263
d s p 8
# I M M 8
d s p 1 6
a b s 1 6
# I M M 1 6
a b s 2 0
d s p 2 0
# I M M 2 0
Rn
An
[An]
b 7
b 7
b 7
b0 b7
L o w - o r d e r 8 b i t s
L o w - o r d e r 8 b i t s
Content at (start address
8 b i t s
Correspondence
dest
+0
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
of instruction+1)
b 0
b 0
b 0
b 7
b 7
M i d d l e- o r d e r 8 b i t s
H i g h- o r d e r 8 b i t s
DEST
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
DEST
+1
Correspondence
b0
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
b 0
b 0
b 7
0 0 0 0
(
dest code
Contents at addresses following
(start address of instruction + 2)
dsp8
+2
dsp16/abs16
dest
H i g h - o r d e r
(See the figure below.)
4 b i t s
4.1
dsp:8[A0]
dsp:8[A1]
dsp:8[SB]
dsp:8[FB]
dsp:16[A0]
dsp:16[A1]
dsp:16[SB]
abs16
b 0
Guide to This Chapter
)
#IMM8
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
DEST
#IMM16