R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 24

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
1.3 Register Configuration
Chapter 1 Overview
The central processing unit (CPU) contains the 13 registers shown in figure 1.3.1. Of these registers, R0,
R1, R2, R3, A0, A1, and FB each consist of two sets of registers configured as two register banks.
Figure 1.3.1 CPU Register Configuration
1.3.1 Data Registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
The data registers (R0, R1, R2, and R3) each consist of 16 bits and are used primarily for transfers and
arithmetic/logic operations.
Registers R0 and R1 can be divided into separate high-order (R0H, R1H) and low-order (R0L, R1L)
parts for use as 8-bit data registers. For some instructions, moreover, R2 and R0 or R3 and R1 can be
combined to configure a 32-bit data register (R2R0 or R3R1).
b31
Note: * These registers configure register banks.This register
bank consists of two sets.
R2
R3
page 4 of 263
b15
IPL
b19
b19
INTBH
INTBH is the upper 4 bits of INTB.
INTBL is the lower 16 bits of INTB.
b15
b15
b15
b15
R0H (High-order of R0)
R1H (High-order of R1)
b8
b7
U
PC
I
INTBL
FLG
USP
ISP
SB
b8 b7
R2
R3
A0
A1
FB
O
R0L (Low-order of R0)
R1L (Low-order of R1)
B
S
Z
D
C
b0
b0
b0
b0
b0
b0
Data register*
Address register*
Frame base register*
Interrupt table register
Program counter
User stack pointer
Interrupt stack pointer
Static base register
Debug flag
Zero flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register
Carry flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
1.3 Register Configuration