MC9S08RD32CDWE Freescale Semiconductor, MC9S08RD32CDWE Datasheet - Page 33

• Manufacturer Part Number: MC9S08RD32CDWE
• Description: IC MCU 32K FLASH 2K RAM 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CDWE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3.6.4
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the
the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when
the MCU enters stop mode so background debug communication is still possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation. The MCU
cannot enter either stop1 mode or stop2 mode if ENBDM is set.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After active background mode is entered, all background
commands are available.
background mode is enabled.
3.6.5
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD reset is enabled in stop by setting the LVDRE bit in SPMSC1 when the CPU
executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user
attempts to enter either stop1 or stop2 with the LVD reset enabled (LVDRE = 1) the MCU will instead
enter stop3.
3.6.6
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks are kept alive to the background debug logic, clocks to
the peripheral systems are halted to reduce power consumption.
Freescale Semiconductor
Mode
Stop3
Mode
Stop3
Don’t
Don’t
PDC
PDC
care
care
Active BDM Enabled in Stop Mode
LVD Reset Enabled
On-Chip Peripheral Modules in Stop Mode
Table 3-3
PPDC
PPDC
Don’t
Don’t
care
care
summarizes the behavior of the MCU in stop when LVD reset is enabled.
Table 3-2
CPU, Digital
Peripherals,
CPU, Digital
Peripherals,
Standby
Standby
FLASH
FLASH
Table 3-2. BDM Enabled Stop Mode Behavior
Table 3-3. LVD Enabled Stop Mode Behavior
Development Support
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
summarizes the behavior of the MCU in stop when entry into the active
Standby
Standby
RAM
RAM
OSC
OSC
On
On
chapter of this data sheet. If ENBDM is set when
Standby
Standby
ACMP
ACMP
Regulator
Regulator
On
On
I/O Pins
I/O Pins
States
States
held
held
Modes of Operation
Optionally on
Optionally on
RTI
RTI
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