S9S08AW60E5MFDE Freescale Semiconductor, S9S08AW60E5MFDE Datasheet - Page 89

• Manufacturer Part Number: S9S08AW60E5MFDE
• Description: MCU 64K FLASH AUTO MONET 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08AW60E5MFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Controller Family/series: HCS08
• No. Of I/o's: 38
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.2
In addition to the I/O control, port A pins are controlled by the registers listed below.
Freescale Semiconductor
PTADD[7:0]
PTAPE[7:0]
Reset
Reset
Field
Field
[7:0]
7:0
W
W
R
R
PTADD7
PTAPE7
Port A Pin Control Registers (PTAPE, PTASE, PTADS)
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
0
0
7
7
PTADD6
PTAPE6
Figure 6-10. Data Direction for Port A Register (PTADD)
0
0
Figure 6-11. Internal Pullup Enable for Port A (PTAPE)
6
6
Table 6-3. PTADD Register Field Descriptions
Table 6-4. PTADD Register Field Descriptions
PTADD5
PTAPE5
0
0
5
5
MC9S08AW60 Data Sheet, Rev 2
PTADD4
PTAPE4
0
0
4
4
Description
Description
PTADD3
PTAPE3
3
0
3
0
PTADD2
PTAPE2
0
0
2
2
Chapter 6 Parallel Input/Output
PTADD1
PTAPE1
0
0
1
1
PTADD0
PTAPE0
0
0
0
0
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