S9S08AW60E5MFDE Freescale Semiconductor, S9S08AW60E5MFDE Datasheet - Page 254

• Manufacturer Part Number: S9S08AW60E5MFDE
• Description: MCU 64K FLASH AUTO MONET 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08AW60E5MFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Controller Family/series: HCS08
• No. Of I/o's: 38
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Chapter 14 Analog-to-Digital Converter (S08ADC10V1)
14.6.1.2
In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit
conversion at low power with a long sample time on input channel 1, where the internal ADCK clock will
be derived from the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
ADCSC2 = 0x00 (%00000000)
ADCSC1 = 0x41 (%01000001)
ADCRH/L = 0xxx
data cannot be overwritten with data from the next conversion.
ADCCVH/L = 0xxx
APCTL1=0x02
APCTL2=0x00
254
Bit 7
Bit 6:5 ADIV
Bit 4
Bit 3:2 MODE
Bit 1:0 ADICLK
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:2
Bit 1:0
Bit 7
Bit 6
Bit 5
Bit 4:0 ADCH
Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion
Holds compare value when compare function enabled
AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins
All other AD pins remain general purpose I/O pins
2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous
software) and compare function options, if enabled.
or completed only once, and to enable or disable conversion complete interrupts. The input channel
on which conversions will be performed is also selected here.
ADLPC
ADLSMP
ADACT
ADTRG
ACFE
ACFGT
COCO
AIEN
ADCO
Pseudo — Code Example
1
00
1
10
00
0
0
0
0
00
00
0
1
0
00001 Input channel 1 selected as ADC input channel
Configures for low power (lowers maximum clock speed)
Sets the ADCK to the input clock ÷ 1
Configures for long sample time
Sets mode at 10-bit conversions
Selects bus clock as input clock source
Flag indicates if a conversion is in progress
Software trigger selected
Compare function disabled
Not used in this example
Unimplemented or reserved, always reads zero
Reserved for Freescale’s internal use; always write zero
Read-only flag which is set when a conversion completes
Conversion complete interrupt enabled
One conversion only (continuous conversions disabled)
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor