MCF51QE96CLH Freescale Semiconductor, MCF51QE96CLH Datasheet - Page 11

• Manufacturer Part Number: MCF51QE96CLH
• Description: IC MCU 32BIT 96K FLASH 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51QEr

Specifications of MCF51QE96CLH

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 20x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: MCF51QE
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 50.33 MHz
• Number Of Programmable I/os: 54
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: EVBQE128, DEMOQE128
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The average chip-junction temperature (T
where:
For most applications, P
is:
Solving
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
for any value of T
3.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Freescale Semiconductor
Equation 1
T
θ
P
P
P
JA
A
D
int
I/O
ESD Protection and Latch-Up Immunity
= Ambient temperature, °C
= P
= Package thermal resistance, junction-to-ambient, °C/W
= I
= Power dissipation on input and output pins — user determined
A
. Using this value of K, the values of P
int
DD
A
+ P
Latch-up
.
Machine
× V
and
Human
Model
Body
I/O
DD
I/O
Equation 2
, Watts — chip internal power
<< P
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
int
and can be neglected. An approximate relationship between P
for K gives:
Table 6. ESD and Latch-up Test Conditions
K = P
J
Description
MCF51QE128 Series Data Sheet, Rev. 7
) in °C can be obtained from:
D
P
T
× (T
D
J
= K ÷ (T
= T
A
D
+ 273°C) + θ
and T
A
+ (P
J
J
+ 273°C)
can be obtained by solving
D
× θ
JA
JA
Symbol
)
R1
R1
× (P
—
—
C
C
D
)
2
Value
1500
– 2.5
100
200
Equation 1
7.5
3
0
3
D
and T
Electrical Characteristics
and
Unit
pF
pF
J
Ω
Ω
Equation 2
V
V
(if P
D
I/O
(at equilibrium)
is neglected)
iteratively
Eqn. 1
Eqn. 2
Eqn. 3
11