mcf51qe128 Freescale Semiconductor, Inc, mcf51qe128 Datasheet

mcf51qe128

Manufacturer Part Number

mcf51qe128

Description

Mcf51qe Flexis 32-bit Coldfire? V1 Microcontroller

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MCF51QE128.pdf (38 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

mcf51qe128CLH

Manufacturer:

Freescale Semiconductor

Quantity:

10 000

Company:

Euro Chip Distribution

Part Number:

mcf51qe128CLH

Quantity:

226

Company:

BOSTOCK HK LIMITED

Part Number:

mcf51qe128CLK

Manufacturer:

Freescale Semiconductor

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

mcf51qe128CLK

Manufacturer:

FREESCALE

Quantity:

20 000

Current page: 1 of 38
Download datasheet (817Kb)

Freescale Semiconductor

Data Sheet: Advance Information

MCF51QE128 Series

Covers: MCF51QE128, MCF51QE64, MCF51QE32

• 32-Bit Version 1 ColdFire

• On-Chip Memory

• Power-Saving Modes

• Clock Source Options

• System Protection

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

– Up to 50.33-MHz ColdFire CPU from 3.6V to 2.1V, and

– Provides 0.94 Dhrystone 2.1 MIPS per MHz

– Implements Instruction Set Revision C (ISA_C)

– Support for up to 30 peripheral interrupt requests and

– Flash read/program/erase over full operating voltage

– Random-access memory (RAM)

– Security circuitry to prevent unauthorized access to

– Two low power stop modes; reduced power wait mode

– Peripheral clock enable register can disable clocks to

– Very low power external oscillator can be used in stop3

– Very low power real time counter for use in run, wait,

– 6 μs typical wake up time from stop modes

– Oscillator (XOSC) — Loop-control Pierce oscillator;

– Internal Clock Source (ICS) — FLL controlled by

– Watchdog computer operating properly (COP) reset

– Low-voltage detection with reset or interrupt; selectable

– Illegal opcode and illegal address detection with

– Flash block protection

20-MHz CPU at 2.1V to 1.8V across temperature range

of -40°C to 85°C

performance when running from internal RAM

(0.76 DMIPS/MHz from flash)

seven software interrupts

and temperature

RAM and flash contents

unused modules, reducing currents; allows clocks to

remain enabled to specific peripherals in stop3 mode

mode to provide accurate clock to active peripherals

and stop modes with internal and external clock sources

Crystal or ceramic resonator range of 31.25 kHz to

38.4 kHz or 1 MHz to 16 MHz

internal or external reference; precision trimming of

internal reference allows 0.2% resolution and 2%

deviation; supports CPU freq. from 2 to 50.33 MHz

with option to run from dedicated 1-kHz internal clock

source or bus clock

trip points

programmable reset or exception response

Central Processor Unit (CPU)

• Development Support

• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion

• ACMPx — Two analog comparators with selectable

• SCIx — Two SCIs with full duplex non-return to zero

• SPIx— Two serial peripheral interfaces with Full-duplex or

• IICx — Two IICs with; Up to 100 kbps with maximum bus

• TPMx — One 6-channel and two 3-channel; Selectable

• RTC — 8-bit modulus counter with binary or decimal

• Input/Output

– Single-wire background debug interface

– 4 PC plus 2 address (optional data) breakpoint registers

– 64-entry processor status and debug data trace buffer

time; automatic compare function; 1.7 mV/°C temperature

sensor; internal bandgap reference channel; operation in

stop3; fully functional from 3.6V to 1.8V

interrupt on rising, falling, or either edge of comparator

output; compare option to fixed internal bandgap reference

voltage; outputs can be optionally routed to TPM module;

operation in stop3

(NRZ); LIN master extended break generation; LIN slave

extended break detection; wake up on active edge

single-wire bidirectional; Double-buffered transmit and

receive; MSB-first or LSB-first shifting

loading; Multi-master operation; Programmable slave

address; Interrupt driven byte-by-byte data transfer;

supports broadcast mode and 10 bit addressing

input capture, output compare, or buffered edge- or

center-aligned PWMs on each channel

based prescaler; External clock source for precise time

base, time-of-day, calendar or task scheduling functions;

Free running on-chip low power oscillator (1 kHz) for

cyclic wake-up without external components

– 70 GPIOs and 1 input-only and 1 output-only pin

– 16 KBI interrupts with selectable polarity

– Hysteresis and configurable pull-up device on all input

– SET/CLR registers on 16 pins (PTC and PTE)

– 16 bits of Rapid GPIO connected to the CPU’s

with programmable 1- or 2-level trigger response

with programmable start/stop conditions

pins; Configurable slew rate and drive strength on all

output pins.

high-speed local bus with set, clear, and toggle

functionality

MCF51QE128

Document Number: MCF51QE128

80-LQFP

Case 917A

14 mm

Rev. 4, 09/2007

64-LQFP

10 mm

Case 840F

Related parts for mcf51qe128

Related keywords

mcf51qe128 datasheet
mcf51qe128 data sheet
mcf51qe128 pdf datasheet
mcf51qe128 component
mcf51qe128 part
mcf51qe128 distributor
mcf51qe128 RoHS
mcf51qe128 datasheet download