MC9S08AC48MFDE Freescale Semiconductor, MC9S08AC48MFDE Datasheet - Page 74
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MC9S08AC48MFDE
Manufacturer Part Number
MC9S08AC48MFDE
Description
MCU 8BIT 48K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC60CFJE.pdf
(348 pages)
Specifications of MC9S08AC48MFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Chapter 5 Resets, Interrupts, and System Configuration
5.9.2
This register includes read-only status flags to indicate the source of the most recent reset. When a debug
host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set.
Writing any value to this register address clears the COP watchdog timer without affecting the contents of
this register. The reset state of these bits depends on what caused the MCU to reset.
74
Any other
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding
to sources that are not active at the time of reset will be cleared.
reset:
POR
LVR:
Field
ILOP
POR
COP
PIN
7
6
5
4
W
R
U = Unaffected by reset
System Reset Status Register (SRS)
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
U
1
0
7
PIN
(1)
0
0
6
Writing any value to SIMRS address clears COP watchdog timer.
Table 5-4. SRS Register Field Descriptions
Figure 5-3. System Reset Status (SRS)
MC9S08AC60 Series Data Sheet, Rev. 2
COP
(1)
0
0
5
ILOP
(1)
0
0
4
Description
Reserved
3
0
0
0
ICG
(1)
0
0
2
Freescale Semiconductor
LVD
1
1
0
1
0
0
0
0
0
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