MC9S08AC48MFDE Freescale Semiconductor, MC9S08AC48MFDE Datasheet - Page 320
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MC9S08AC48MFDE
Manufacturer Part Number
MC9S08AC48MFDE
Description
MCU 8BIT 48K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC60CFJE.pdf
(348 pages)
Specifications of MC9S08AC48MFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Appendix A Electrical Characteristics and Timing Specifications
A.10
This section describes ac timing characteristics for each peripheral system. For detailed information about
how clocks for the bus are generated, see
A.10.1
320
1
2
3
4
5
Num
Typical values are based on characterization data at V
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on
the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
1
2
4
6
8
3
5
7
9
AC Characteristics
C
Control Timing
Bus frequency (t
Real-time interrupt internal oscillator period
External reset pulse width
(t
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ pulse width
KBIPx pulse width
Port rise and fall time —
High output drive (PTxDS) (load = 50 pF)
cyc
Asynchronous path
Synchronous path
Asynchronous path
Synchronous path
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
= 1/f
RESET PIN
Self_reset
3
cyc
)
Parameter
= 1/f
4
3
2
2
Bus
MC9S08AC60 Series Data Sheet, Rev. 2
DD
2
)
and 80% V
Figure A-10. Reset Timing
Table A-12. Control Timing
Chapter 10, “Internal Clock Generator
DD
DD
5
levels. Temperature range –40°C to 125°C.
= 5.0V, 25°C unless otherwise stated.
t
extrst
t
t
t
Symbol
Rise
ILIH,
ILIH,
t
t
t
MSSU
t
rstdrv
f
t
extrst
MSH
Bus
RTI
, t
t
t
IHIL
IHIL
Fall
t
1.5 x t
1.5 x t
34 x t
Self_reset
1.5 x
Min
700
100
100
dc
25
25
—
—
cyc
cyc
cyc
Typ
(S08ICGV4).”
—
—
—
30
3
1
Freescale Semiconductor
1300
Max
20
—
—
—
—
—
—
MHz
Unit
μs
ns
ns
ns
ns
ns
ns
ns
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