MC9S08AC48MFDE Freescale Semiconductor, MC9S08AC48MFDE Datasheet - Page 58
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MC9S08AC48MFDE
Manufacturer Part Number
MC9S08AC48MFDE
Description
MCU 8BIT 48K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC60CFJE.pdf
(348 pages)
Specifications of MC9S08AC48MFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Chapter 4 Memory
58
Reset
PRDIV8
DIV[5:0]
DIVLD
Field
7
6
5
W
R
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5 μs
to 6.7 μs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See
DIV5:DIV0 for selected bus frequencies.
0
7
200 kHz
150 kHz
20 MHz
10 MHz
8 MHz
4 MHz
2 MHz
1 MHz
f
Bus
= Unimplemented or Reserved
PRDIV8
if PRDIV8 = 1 — f
(Binary)
PRDIV8
if PRDIV8 = 0 — f
0
6
Figure 4-4. FLASH Clock Divider Register (FCDIV)
1
0
0
0
0
0
0
0
Equation 4-1
Table 4-7. FLASH Clock Divider Settings
Table 4-6. FCDIV Field Descriptions
MC9S08AC60 Series Data Sheet, Rev. 2
DIV5
DIV5:DIV0
(Decimal)
0
5
FCLK
12
49
39
19
9
4
0
0
FCLK
and
= f
Equation
= f
Bus
DIV4
Bus
0
4
192.3 kHz
÷ (8 × ([DIV5:DIV0] + 1))
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
150 kHz
f
FCLK
Description
÷ ([DIV5:DIV0] + 1)
4-2.
Table 4-7
DIV3
3
0
Program/Erase Timing Pulse
shows the appropriate values for PRDIV8 and
(5 μs Min, 6.7 μs Max)
DIV2
5.2 μs
6.7 μs
0
5 μs
5 μs
5 μs
5 μs
5 μs
5 μs
2
Freescale Semiconductor
DIV1
0
1
Eqn. 4-1
Eqn. 4-2
DIV0
0
0
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