S9S08SG8E2MTJ Freescale Semiconductor, S9S08SG8E2MTJ Datasheet - Page 33

• Manufacturer Part Number: S9S08SG8E2MTJ
• Description: MCU 2K FLASH 20-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG8E2MTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1
2
Table 3-1
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
counter (RTC), LVD system, ACMP, ADC, SCI, or any pin interrupts.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.1.1
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. For configuring the LVD system for interrupt or reset, refer to
(LVD)
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate in stop mode, the LVD must be enabled when entering stop3.
For the ACMP to operate in stop mode with compare to internal bandgap option, the LVD must be enabled
when entering stop3.
3.6.1.2
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation.
Freescale Semiconductor
STOPE
ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see
Control Register
When in Stop3 mode with BDM enabled, The S
0
1
1
1
1
System”. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
shows all of the control bits that affect stop mode selection and the mode selected under various
ENBDM
Stop3 Mode
LVD Enabled in Stop Mode
Active BDM Enabled in Stop Mode
1
0
0
0
x
(BDCSCR)”.
1
Both bits must be 1
LVDE
Either bit a 0
Either bit a 0
Chapter 17, “Development
x
x
LVDSE
MC9S08SG8 MCU Series Data Sheet, Rev. 6
Table 3-1. Stop Mode Selection
PPDC
x
x
0
0
1
IDD
will be near R
Stop modes disabled; illegal opcode reset if STOP instruction executed
Stop3 with BDM enabled
Stop3
Stop2
Stop3 with voltage regulator active
Support.” If ENBDM is set when the CPU executes a
IDD
levels because internal clocks are enabled.
2
Stop Mode
Section 17.4.1.1, “BDC Status and
5.6, “Low-Voltage Detect
Chapter 3 Modes of Operation
Table
3-1. The
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