S9S08SG8E2MTJ Freescale Semiconductor, S9S08SG8E2MTJ Datasheet
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MC9S08SG8 MC9S08SG4 Data Sheet HCS08 Microcontrollers MC9S08SG8 Rev. 6 7/2009 freescale.com ...
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MC9S08SG8 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • HC08 instruction set with added BGND instruction • Support for interrupt/reset sources On-Chip Memory • FLASH read/program/erase over full operating ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006-2009. All rights reserved. MC9S08SG8 Data Sheet Covers MC9S08SG8 MC9S08SG4 MC9S08SG8 Rev. 6 7/2009 ...
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... Rebuilt book to ensure proper footers and pagination. • Revised all "Reserved" vector space memory locations in Table 4-1 to read, "Unused Vector Space (available for user program)." © Freescale Semiconductor, Inc., 2006-2008. All rights reserved. This product incorporates SuperFlash 6 Description of Changes ° ...
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... Serial Communications Interface (S08SCIV4)..................... 199 Chapter 15 Serial Peripheral Interface (S08SPIV3) ................................ 219 Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) ......................... 235 Chapter 17 Development Support ........................................................... 263 Appendix A Electrical Characteristics...................................................... 285 Appendix B Ordering Information and Mechanical Drawings................ 313 Freescale Semiconductor Contents Title MC9S08SG8 MCU Series Data Sheet, Rev. 6 Page 7 ...
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... MC9S08SG8 Series Memory Map .................................................................................................36 4.2 Reset and Interrupt Vector Assignments .........................................................................................37 4.3 Register Addresses and Bit Assignments ........................................................................................38 4.4 RAM ................................................................................................................................................45 4.5 FLASH ............................................................................................................................................45 4.5.1 Features .............................................................................................................................46 4.5.2 Program and Erase Times .................................................................................................46 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections Chapter 3 Modes of Operation Chapter 4 Memory MC9S08SG8 MCU Series Data Sheet, Rev ...
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... System Power Management Status and Control 2 Register (SPMSC2) ...........................71 6.1 Port Data and Data Direction ..........................................................................................................72 6.2 Pull-up, Slew Rate, and Drive Strength ...........................................................................................73 6.3 Ganged Output ................................................................................................................................74 6.4 Pin Interrupts ...................................................................................................................................75 10 Title Chapter 5 Chapter 6 Parallel Input/Output Control MC9S08SG8 MCU Series Data Sheet, Rev. 6 Page Freescale Semiconductor ...
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... HCS08 Instruction Set Summary ....................................................................................................97 5-V Analog Comparator (S08ACMPV2) 8.1 Introduction ...................................................................................................................................109 8.1.1 ACMP Configuration Information ..................................................................................109 8.1.2 ACMP in Stop3 Mode .....................................................................................................109 8.1.3 ACMP/TPM Configuration Information .........................................................................109 8.1.4 Features ...........................................................................................................................111 Freescale Semiconductor Title Chapter 7 Chapter 8 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Page 11 ...
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... Automatic Compare Function .........................................................................................136 9.4.6 MCU Wait Mode Operation ............................................................................................136 9.4.7 MCU Stop3 Mode Operation ..........................................................................................136 9.4.8 MCU Stop1 and Stop2 Mode Operation .........................................................................137 12 Title Chapter 9 ) ..................................................................................................123 DDAD ) .................................................................................................123 SSAD ) ...................................................................................123 REFH ) .....................................................................................123 REFL MC9S08SG8 MCU Series Data Sheet, Rev. 6 Page Freescale Semiconductor ...
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... SDA — Serial Data Line ................................................................................................162 11.3 Register Definition ........................................................................................................................162 11.3.1 IIC Address Register (IICA) ...........................................................................................163 11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................163 11.3.3 IIC Control Register (IICC1) ..........................................................................................166 Freescale Semiconductor Title Chapter 10 Chapter 11 MC9S08SG8 MCU Series Data Sheet, Rev. 6 ...
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... Register Definition ........................................................................................................................192 13.3.1 RTC Status and Control Register (RTCSC) ....................................................................193 13.3.2 RTC Counter Register (RTCCNT) ..................................................................................194 13.3.3 RTC Modulo Register (RTCMOD) ................................................................................194 13.4 Functional Description ..................................................................................................................194 14 Title Chapter 12 Modulo Timer (S08MTIMV1) Chapter 13 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Page Freescale Semiconductor ...
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... Register Definition ........................................................................................................................225 15.4.1 SPI Control Register 1 (SPIC1) ......................................................................................225 15.4.2 SPI Control Register 2 (SPIC2) ......................................................................................226 15.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................227 15.4.4 SPI Status Register (SPIS) ..............................................................................................228 Freescale Semiconductor Title Chapter 14 Chapter 15 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Page ...
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... Forcing Active Background ............................................................................................263 17.1.2 Features ...........................................................................................................................264 17.2 Background Debug Controller (BDC) ..........................................................................................264 17.2.1 BKGD Pin Description ...................................................................................................265 17.2.2 Communication Details ..................................................................................................266 17.2.3 BDC Commands .............................................................................................................270 16 Title Chapter 16 Chapter 17 Development Support MC9S08SG8 MCU Series Data Sheet, Rev. 6 Page Freescale Semiconductor ...
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... A.14 EMC Performance .........................................................................................................................312 A.14.1 Radiated Emissions .........................................................................................................312 Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................313 B.1.1 Device Numbering Scheme ............................................................................................313 B.2 Package Information and Mechanical Drawings ..........................................................................313 Freescale Semiconductor Title Appendix A Electrical Characteristics Appendix B MC9S08SG8 MCU Series Data Sheet, Rev. 6 ...
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... Pin quantity ACMP ADC channels DBG ICS IIC MTIM Pin Interrupts Pin I/O RTC SCI SPI TPM1 channels TPM2 channels XOSC 1 FBE and FEE modes are not available in 8-pin packages. Freescale Semiconductor t 9S08SG8 8192 512 yes yes 1 yes yes yes yes ...
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... REFH MC9S08SG8 MCU Series Data Sheet, Rev. 6 PTA3/PAI3/SCL/ADP3 PTA2/PAI2/SDA/ADP2/ACMPO PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ SEE NOTE 1, 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTB3/PIB3/MOSI/ADP7 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 PTB0/PIB0/RxD/ADP4 SEE NOTE 1, 2 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 /V , are double bonded to V and V respectively. SSA REFL DD SS Freescale Semiconductor ...
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... Analog Comparator (5V) Analog-to-Digital Converter Central Processor Unit Inter-Integrated Circuit Internal Clock Source Serial Peripheral Interface Serial Communications Interface Modulo Timer Real-Time Counter Timer Pulse Width Modulator Freescale Semiconductor Table 1-2. Module Versions Module (ACMP) (ADC) (CPU) (IIC) (ICS) (SPI) (SCI) (MTIM) ...
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... MC9S08SG8 MCU Series Data Sheet, Rev. 6 MTIM SCI SPI IIC FLASH ADC ADC has min and max FLASH has frequency frequency requirements. requirements for program See the ADC chapter and erase operation. See and electricals appendix the electricals appendix for details. for details. Freescale Semiconductor ...
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... Device Pin Assignment Figure 2-1 - Figure 2-3 shows the pin assignments for the MC9S08SG8 Series devices. RESET BKGD/MS V PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/ADP11 PTC2/ADP10 RESET BKGD/MS V PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO Freescale Semiconductor PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP PTA1/PIA1/TPM2CH0/ADP1/ACMP PTA2/PIA2/SDA/ADP2/ACMPO PTA3/PIA3/SCL/ADP3 PTB0/PIB0/RxD/ADP4 PTB1/PIB1/TxD/ADP5 7 ...
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... Chapter 2 Pins and Connections BKGD/MS 23 RESET PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP PTA1/PIA1/TPM2CH0/ADP1/ACMP PTA2/PIA2/SDA/ADP2/ACMPO PTA3/PIA3/SCL/ADP3 Figure 2-3. 8-Pin SOIC MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
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... CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage Freescale Semiconductor MC9S08SG8 Se- BKGD/MS ...
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... This pin does not contain a clamp diode to V above Chapter 10, “Internal Clock Source (when used) and R S NOTE and should not be driven DD MC9S08SG8 MCU Series Data Sheet, Rev. 6 should be low-inductance F Freescale Semiconductor ...
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... For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output Freescale Semiconductor level an external pullup should DD NOTE for an example. Control.” ...
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... B and port C pins to outputs so the pins do not float. When using the 16-pin devices, the user must either enable on-chip pullup devices or change the direction of non-bonded out port C pins to outputs so the pins do not float. 27 NOTE MC9S08SG8 MCU Series Data Sheet, Rev. 6 Section Freescale Semiconductor ...
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... The output data, drive strength and slew-rate control of this port pin will follow the configuration for the PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out. Ganged output not available in 8-pin packages ACMP and ADC are both enabled, both will have access to the pin. Freescale Semiconductor Priority Lowest Port Pin Alt 1 ...
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... Chapter 2 Pins and Connections 29 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
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... When encountering a BDC breakpoint • When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 (SBDFR)”) 30 ...
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... MCU is operated in run mode for the first time. When the MC9S08SG8 Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed ...
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... STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. Freescale Semiconductor Table 3-1. Stop Mode Selection PPDC x Stop modes disabled ...
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... Refer to Mode,” and Section 3.6.1, “Stop3 33 Mode,” for specific information on system behavior in stop modes. MC9S08SG8 MCU Series Data Sheet, Rev. 6 Table 3-1. Most is below the LVD DD Section 3.6.2, “Stop2 Freescale Semiconductor ...
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... Voltage regulator will BDM is enabled or if LVD is enabled when entering stop3. 7 ERCLKEN and EREFSTEN set in ICSC2, else in standby. For high frequency range (RANGE in ICSC2 set) requires the LVD to also be enabled in stop3. Freescale Semiconductor Table 3-2. Stop Mode Behavior Mode Stop2 Off ...
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... Chapter 3 Modes of Operation 35 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
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... DIRECT PAGE REGISTERS 0x007F 0x0080 0x027F 0x0280 0x17FF 0x1800 HIGH PAGE REGISTERS 0x185F 0x1860 0xDFFF 0xE000 0xFFFF Figure 4-1. MC9S08SG8 Series Memory Map Freescale Semiconductor 0x0000 0x007F 0x0080 RAM 0x017F 512 BYTES 0x0180 0x027F 0x0280 UNIMPLEMENTED 5504 BYTES 0x17FF 0x1800 0x185F ...
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... Chapter 4 Memory 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor provided equate file for the MC9S08SG8 Series. Address (High/Low) 0xFFC0:0xFFC1 0xFFC2:0xFFC3 ...
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... Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. Freescale Semiconductor can use the more efficient direct addressing mode, which requires 4-4, the whole address in column one is shown in bold. In MC9S08SG8 MCU Series Data Sheet, Rev ...
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... ELS0B ELS0A ELS1B ELS1A — — — — — — SBR11 SBR10 SBR9 Freescale Semiconductor Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 — — ACMOD0 — — ADR8 ADR0 ADCV8 ADCV0 ADPC0 ADPC8 — — 0 PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 ...
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... TOF 0x0061 TPM2CNTH Bit 15 0x0062 TPM2CNTL Bit 7 0x0063 TPM2MODH Bit 15 0x0064 TPM2MODL Bit 7 0x0065 TPM2C0SC CH0F 0x0066 TPM2C0VH Bit 15 0x0067 TPM2C0VL Bit 7 0x0068 TPM2C1SC CH1F Freescale Semiconductor SBR6 SBR5 SBR4 SCISWAI RSRC M TCIE RIE ILIE TC RDRF IDLE RXEDGIF 0 RXINV T8 TXDIR TXINV — ...
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... Reserved 0x007F — — — — RTCLKS RTIE RTCCNT RTCMOD — — — — — — MC9S08SG8 MCU Series Data Sheet, Rev — — — RTCPS — — — — — — Freescale Semiconductor Bit 0 Bit 8 Bit 0 — — — ...
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... Reserved 0x183F — 0x1840 PTAPE 0 0x1841 PTASE 0 0x1842 PTADS 0 0x1843 Reserved — 0x1844 PTASC 0 Freescale Semiconductor 4-3, are accessed much less often than other I/O and control registers PIN COP ILOP COPT STOPE 0 COPW 0 ACIC — — — ...
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... PTBPS3 PTBPS2 PTBPS1 PTBPS0 PTBES3 PTBES2 PTBES1 PTBES0 — — — PTCPE3 PTCPE2 PTCPE1 PTCPE0 PTCSE3 PTCSE2 PTCSE1 PTCSE0 PTCDS3 PTCDS2 PTCDS1 PTCDS0 GNGPS3 GNGPS2 GNGPS1 GNGEN — — — — — — Freescale Semiconductor Bit 0 — — — — — ...
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... FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC) to the unsecured state (1:0). Freescale Semiconductor Table 4-4, are located in the FLASH memory. These registers Table 4-4 ...
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... MC9S08SG8 Series usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX #RamLast+1 ...
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... Parameter Byte program Byte program (burst) Page erase Mass erase 1 Excluding start/end overhead Freescale Semiconductor (FCDIV)”). This register can be written only ) is used by the command processor to time FCLK = 1/f FCLK FCLK Table 4-5. Program and Erase Times Cycles of FCLK ...
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... FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. 47 NOTE Figure 4 flowchart for executing all of the commands except for MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
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... The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. Freescale Semiconductor WRITE TO FCDIV (Note 1) START ...
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... WRITE COMMAND (0x25) TO FCMD WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles before TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) YES FPVIO OR FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE MC9S08SG8 MCU Series Data Sheet, Rev. 6 checking FCBEF or FCCF. ERROR EXIT Freescale Semiconductor ...
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... For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), the FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of NVPROT) must Freescale Semiconductor NVPROT)”). Figure 4-4 ...
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... NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state disengages security and the other three combinations engage security. Notice the erased state (1:1) makes 51 1 A12 A11 A10 A9 A8 Figure 4-4. Block Protection Mechanism MC9S08SG8 MCU Series Data Sheet, Rev Freescale Semiconductor ...
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... FLASH Registers and Control Bits The FLASH module has nine 8-bit registers in the high-page register space, two locations (NVOPT, NVPROT) in the nonvolatile register space in FLASH memory are copied into corresponding high-page Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 4 Memory ...
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... Refer to Table 4-3 and Table 4-4 refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.7.1 FLASH Clock Divider Register (FCDIV) Bit 7 of this register is a read-only flag. Bits 6:0 may be read at any time but can be written only one time. ...
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... MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the background debug interface. SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. For more detailed information about security, refer to Freescale Semiconductor Table 4-7. FLASH Clock Divider Settings DIV f ...
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... Background commands can be used to change the contents of these bits in FPROT. Figure 4-8. FLASH Protection Register (FPROT) 55 Table 4-9. Security States SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure KEYACC Description Section 4. (1) FPS MC9S08SG8 MCU Series Data Sheet, Rev “Security.” Freescale Semiconductor (1) FPDIS ...
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... Protection Violation Flag — FPVIOL is set automatically when a command is written that attempts to erase or FPVIOL program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing FPVIOL protection violation attempt was made to erase or program a protected location. Freescale Semiconductor Description 5 4 FPVIOL FACCERR ...
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... Execution,” for a detailed discussion of FLASH programming and FCMD Table 4-13. FLASH Commands FCMD 0x05 0x20 0x25 0x40 0x41 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Errors.” FACCERR is cleared by Table 4-13. Refer Equate File Label mBlank mByteProg mBurstProg mPageErase mMassErase Freescale Semiconductor Section ...
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... Illegal opcode detect (ILOP) • Illegal address detect (ILAD) • Background debug forced reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Table 5-2) 58 ...
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... LPO LPO MC9S08SG8 MCU Series Data Sheet, Rev. 6 (SOPT1),” (SOPT2),” for additional COP Overflow Count COP is disabled cycles ( cycles (256 cycles (1.024 cycles 16 2 cycles 18 2 cycles Section A.12.1, “Control Timing,” for the Freescale Semiconductor ...
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... ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is not recommended for anyone Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control MC9S08SG8 MCU Series Data Sheet, Rev. 6 ...
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... INDEX REGISTER (LOW BYTE PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08SG8 MCU Series Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
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... CCR the CPU will finish the current instruction; stack the PCL, PCH and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control MC9S08SG8 MCU Series Data Sheet, Rev. 6 ...
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... CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 — — LVWIE Low-voltage warning — — — Software interrupt COPT Watchdog timer LVDRE Low-voltage detect — External pin Illegal opcode — — Illegal address Freescale Semiconductor ...
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... Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control in Chapter 4, “ ...
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... ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode COP ILOP ILAD (2) (2) Note Note Note Figure 5-2. System Reset Status (SRS) Table 5-3. SRS Register Field Descriptions Description MC9S08SG8 MCU Series Data Sheet, Rev LVD ( Freescale Semiconductor ...
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... Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Table 5-3. SRS Register Field Descriptions Description ...
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... IIC Pin Select — This bit selects the location of the SDA and SCL pins of the IIC module. IICPS 0 SDA on PTA2, SCL on PTA3. 1 SDA on PTB6, SCL on PTB7 STOPE 0 0 Table 5-5. SOPT1 Register Field Descriptions Description MC9S08SG8 MCU Series Data Sheet, Rev IICPS Table 5-1. Freescale Semiconductor ...
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... T1CH1PS 0 TPM1CH1 on PTB5. 1 TPM1CH1 on PTC1. 0 TPM1CH0 Pin Select— This bit selects the location of the TPM1CH0 pin of the TPM1 module. T1CH0PS 0 TPM1CH0 on PTA0. 1 TPM1CH0 on PTC0. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ACIC 0 0 Table 5-6. SOPT2 Register Field Descriptions Description MC9S08SG8 MCU Series Data Sheet, Rev ...
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... ID11 — — Table 5-7. SDIDH Register Field Descriptions Description 5 4 ID5 ID4 0 1 Table 5-8. SDIDL Register Field Descriptions Description MC9S08SG8 MCU Series Data Sheet, Rev ID10 ID9 Table 5- ID3 ID2 ID1 Table 5-7. Freescale Semiconductor 0 ID8 0 0 ID0 0 ...
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... Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the BGBE ADC module on one of its internal channels or ACMP on its ACMP+ input. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ...
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... See Electrical Characteristics appendix for minimum and maximum values PPDF 1 LVDV LVWV Description Table 5-11. LVW Trip Point V = 2.74 V LVW0 V = 2.92 V LVW1 V = 4.3 V LVW2 V = 4.6 V LVW3 MC9S08SG8 MCU Series Data Sheet, Rev PPDC PPDACK Unaffected by reset 1 LVD Trip Point V = 2.56 V LVD0 V = 4.0 V LVD1 Freescale Semiconductor 2 ...
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... In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. Freescale Semiconductor 2-1. The peripheral modules have priority over the general-purpose I/O NOTE Figure MC9S08SG8 MCU Series Data Sheet, Rev ...
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... Because of this, the EMC emissions may be affected by enabling pins as high drive. 73 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram MC9S08SG8 MCU Series Data Sheet, Rev. 6 Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
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... Ganged output not available on 8-pin packages. PTC3-PTC0 not available on 16-pin packages, however PTC0 control registers are still used to control ganged output. 2 When GNGEN = 1, PTC0 is forced to an output, regardless of the value in PTCDD0 in PTCDD. Freescale Semiconductor NOTE Table 2-1 for information on pin priority. ...
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... PTxACK. 75 Figure 6- CLR PORT INTERRUPT FF PTxMOD Figure 6-2. Pin Interrupt Block Diagram MC9S08SG8 MCU Series Data Sheet, Rev. 6 BUSCLK PTxACK RESET PTxIF SYNCHRONIZER STOP BYPASS PTx STOP INTERRUPT REQUEST PTxIE Freescale Semiconductor ...
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... I/O and their pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 6 Parallel Input/Output Control 76 ...
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... Output driver enabled for port A bit n and PTAD reads return the contents of PTADn PTAD3 0 0 Figure 6-3. Port A Data Register (PTAD) Table 6-2. PTAD Register Field Descriptions Description PTADD3 0 0 Description MC9S08SG8 MCU Series Data Sheet, Rev PTAD2 PTAD1 PTADD2 PTADD1 Freescale Semiconductor 0 PTAD0 0 0 PTADD0 0 ...
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... Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control 3:0 is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. PTASE[3:0] 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. Freescale Semiconductor PTAPE3 R ...
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... Port A Detection Mode — PTAMOD (along with the PTAES bits) controls the detection mode of the port A PTAMOD interrupt pins. 0 Port A pins detect edges only. 1 Port A pins detect both edges and levels PTADS3 Description PTAIF Description MC9S08SG8 MCU Series Data Sheet, Rev PTADS2 PTADS1 PTADS0 PTAIE PTAMOD PTAACK Freescale Semiconductor ...
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... Port A Edge Selects — Each of the PTAESn bits serves a dual purpose by selecting the polarity of the active PTAES[3:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. Freescale Semiconductor ...
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... Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn PTBD5 PTBD4 PTBD3 Figure 6-11. Port B Data Register (PTBD) Description PTBDD5 PTBDD4 PTBDD3 Description MC9S08SG8 MCU Series Data Sheet, Rev PTBD2 PTBD1 PTBD0 PTBDD2 PTBDD1 PTBDD0 Freescale Semiconductor ...
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... Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control PTBSE[7:0] is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. Freescale Semiconductor PTBPE5 ...
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... Port B Detection Mode — PTBMOD (along with the PTBES bits) controls the detection mode of the port B PTBMOD interrupt pins. 0 Port B pins detect edges only. 1 Port B pins detect both edges and levels PTBDS5 PTBDS4 PTBDS3 Description PTBIF Description MC9S08SG8 MCU Series Data Sheet, Rev PTBDS2 PTBDS1 PTBDS0 PTBIE PTBMOD PTBACK Freescale Semiconductor ...
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... Port B Edge Selects — Each of the PTBESn bits serves a dual purpose by selecting the polarity of the active PTBES[3:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. Freescale Semiconductor ...
Page 86
... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn PTCD3 Figure 6-19. Port C Data Register (PTCD) Description PTCDD3 Description MC9S08SG8 MCU Series Data Sheet, Rev PTCD2 PTCD1 PTCD0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...
Page 87
... Output Slew Rate Enable for Port C Bits — Each of these control bits determines if the output slew rate control PTCSE[3:0] is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. Freescale Semiconductor ...
Page 88
... Ganged Output Drive Enable Bit— This write-once control bit selects whether the ganged output drive feature GNGEN is enabled. 0 Ganged output drive disabled. 1 Ganged output drive enabled. PTC0 forced to output regardless of the value of PTCDD0 in PTCDD PTCDS3 Description GNGPS5 GNGPS4 GNGPS3 Description MC9S08SG8 MCU Series Data Sheet, Rev PTCDS2 PTCDS1 PTCDS0 GNGPS2 GNGPS1 GNGEN Freescale Semiconductor ...
Page 89
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler effi ...
Page 90
... For compatibility with the earlier M68HC05 Family forced to 0x00 during reset. Reset has no effect on the contents ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 91
... Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. CONDITION CODE REGISTER Freescale Semiconductor ...
Page 92
... Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location 92 Table 7-1. CCR Register Field Descriptions Description MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 93
... Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 7 Central Processor Unit (S08CPUV2) ...
Page 94
... The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU circuitry. This section provides additional information about these operations. 94 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 95
... The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program not asynchronous to program execution. Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08SG8 MCU Series Data Sheet, Rev. 6 ...
Page 96
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. 96 chapter for more details. MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 97
... ASL opr8a ASLA ASLX C ASL oprx8,X b7 ASL ,X ASL oprx8,SP (Same as LSL) ASR opr8a Arithmetic Shift Right ASRA ASRX ASR oprx8,X ASR , ASR oprx8,SP Freescale Semiconductor Object Code IMM DIR EXT IX2 IX1 IX SP2 9E D9 SP1 9E E9 IMM DIR EXT IX2 IX1 IX ...
Page 98
... Freescale Semiconductor ...
Page 99
... Clear Interrupt Mask Bit (I ← 0) CLI M ← $00 CLR opr8a Clear A ← $00 CLRA X ← $00 CLRX H ← $00 CLRH M ← $00 CLR oprx8,X M ← $00 CLR ,X M ← $00 CLR oprx8,SP Freescale Semiconductor Object Code REL 2A rr REL 20 rr DIR (b0) 01 DIR (b1) 03 DIR (b2) 05 DIR (b3) 07 DIR (b4) 09 DIR (b5) ...
Page 100
... Freescale Semiconductor ...
Page 101
... Logical Shift Left LSLA LSLX C LSL oprx8,X b7 LSL ,X (Same as ASL) LSL oprx8,SP LSR opr8a Logical Shift Right LSRA LSRX 0 LSR oprx8,X LSR ,X b7 LSR oprx8,SP Freescale Semiconductor Object Code DIR INH INH IX1 IX SP1 9E 6C DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 ...
Page 102
... Freescale Semiconductor ...
Page 103
... Enable Interrupts: Stop Processing STOP Refer to MCU Documentation I bit ← 0; Stop Processing STX opr8a STX opr16a STX oprx16,X Store X (Low 8 Bits of Index Register) STX oprx8,X in Memory M ← (X) STX ,X STX oprx16,SP STX oprx8,SP Freescale Semiconductor Object Code INH 9C INH 80 INH 81 IMM A2 DIR B2 EXT C2 ...
Page 104
... Freescale Semiconductor ...
Page 105
... Concatenated with CCR Bits: V Overflow bit H Half-carry bit I Interrupt mask N Negative bit Z Zero bit C Carry/borrow bit Freescale Semiconductor Object Code INH 94 INH 8F Addressing Modes: DIR Direct addressing mode EXT Extended addressing mode IMM Immediate addressing mode INH Inherent addressing mode ...
Page 106
... IMM 2 DIR 3 EXT 3 IX2 TXA AIX STX STX STX INH 2 IMM 2 DIR 3 EXT 3 IX2 Opcode HCS08 Cycles Hexadecimal SUB Instruction Mnemonic Addressing Mode Number of Bytes 1 IX Freescale Semiconductor SUB SUB 2 IX1 CMP CMP 2 IX1 SBC SBC 2 IX1 CPX CPX 2 IX1 1 IX ...
Page 107
... EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control 9E60 6 NEG 3 SP1 9E61 6 CBEQ 4 SP1 ...
Page 108
... Chapter 7 Central Processor Unit (S08CPUV2) 108 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 109
... The ACMP module can be configured to connect the output of the analog comparator to TPM1 input capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPM1CH0 pin is not available externally regardless of the configuration of the TPM1 module for channel 0. Freescale Semiconductor Section 5.7.6, “System Power Management Status and Control 1 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Section A.6, “ ...
Page 110
... REFH MC9S08SG8 MCU Series Data Sheet, Rev. 6 PTA3/PAI3/SCL/ADP3 PTA2/PAI2/SDA/ADP2/ACMPO PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ SEE NOTE 1, 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTB3/PIB3/MOSI/ADP7 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 PTB0/PIB0/RxD/ADP4 SEE NOTE 1, 2 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 /V , are double bonded to V and V respectively. SSA REFL DD SS Freescale Semiconductor ...
Page 111
... ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP will continue to operate normally. 8.1.6 Block Diagram The block diagram for the Analog Comparator module is shown Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 8 Analog Comparator (S08ACMPV2) Figure 8-2. ...
Page 112
... Chapter 8 Analog Comparator (S08ACMPV2) Internal Reference ACMP+ ACMP- Figure 8-2. Analog Comparator 5V (ACMP5) Block Diagram 112 Internal Bus ACBGS Status & Control ACME Register + Interrupt Control - Comparator MC9S08SG8 MCU Series Data Sheet, Rev. 6 ACMP INTERRUPT REQUEST ACIE ACF ACOPE ACMPO Freescale Semiconductor ...
Page 113
... Refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all ACMP registers.This section refers to registers and control bits only by their names . Some MCUs may have more than one ACMP, so register names include placeholder characters to identify which ACMP is being referenced. Freescale Semiconductor Table 8-1. Table 8-1. Signal Properties Function Inverting analog input to the ACMP ...
Page 114
... ACMOD 00 Encoding 0 — Comparator output falling edge 01 Encoding 1 — Comparator output rising edge 10 Encoding 2 — Comparator output falling edge 11 Encoding 3 — Comparator output rising or falling edge 114 ACO ACF ACIE Description MC9S08SG8 MCU Series Data Sheet, Rev ACOPE ACMOD Freescale Semiconductor ...
Page 115
... The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPO pin using ACOPE. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 8 Analog Comparator (S08ACMPV2) ...
Page 116
... Chapter 8 Analog Comparator (S08ACMPV2) 116 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 117
... AD13 01110 AD14 01111 AD15 1 For information, see Section 9.1.4, “Temperature 2 Requires BGBE =1 in SPMSC1 see For value of bandgap voltage reference see Freescale Semiconductor NOTE Table 9-1. ADC Channel Assignment Input ADCH PTA0/ADP0 PTA1/ADP1 PTA2/ADP2 PTA3/ADP3 PTB0/ADP4 PTB1/ADP5 PTB2/ADP6 PTB3/ADP7 ...
Page 118
... V/°C. 118 ) after being divided down from the ALTCLK input as ADCK . For value of bandgap voltage, see DD , convert the digital value of AD26 into a voltage ÷ (( TEMP TEMP25 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Section A.6, “DC V TEMP Eqn. 9-1 Freescale Semiconductor ...
Page 119
... Once determined if the temperature is above or below 25°C, the user can recalculate the temperature using the hot or cold slope value obtained during calibration. Figure 9-1 shows the MC9S08SG8 block diagram with the ADC module highlighted. Freescale Semiconductor and m values from the ADC Electricals table. TEMP25 , the cold slope value is applied in ...
Page 120
... REFH MC9S08SG8 MCU Series Data Sheet, Rev. 6 PTA3/PAI3/SCL/ADP3 PTA2/PAI2/SDA/ADP2/ACMPO PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ SEE NOTE 1, 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTB3/PIB3/MOSI/ADP7 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 PTB0/PIB0/RxD/ADP4 SEE NOTE 1, 2 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 /V , are double bonded to V and V respectively. SSA REFL DD SS Freescale Semiconductor ...
Page 121
... Selectable asynchronous hardware conversion trigger. • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value. 9.1.6 Block Diagram Figure 9-2 provides a block diagram of the ADC module Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08SG8 MCU Series Data Sheet, Rev. 6 121 ...
Page 122
... Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL Analog power supply V DDAD V Analog ground SSAD MC9S08SG8 MCU Series Data Sheet, Rev. 6 Async Clock Gen ADACK Bus Clock ÷2 ALTCLK 1 AIEN Interrupt 2 COCO 3 Freescale Semiconductor ...
Page 123
... Status and Control Register 1 (ADCSC1) This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). Freescale Semiconductor ) DDAD as its power connection. In some packages, V ...
Page 124
... Figure 9-4. Input Channel Select Input Select AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 MC9S08SG8 MCU Series Data Sheet, Rev ADCH ADCH Input Select 10000 AD16 10001 AD17 10010 AD18 10011 AD19 10100 AD20 10101 AD21 10110 AD22 10111 AD23 Freescale Semiconductor ...
Page 125
... Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Input Select AD8 AD9 ...
Page 126
... In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data in ADCRL becomes invalid. 126 Description MC9S08SG8 MCU Series Data Sheet, Rev ADR9 ADR8 Freescale Semiconductor ...
Page 127
... ADCV6 W Reset Figure 9-9. Compare Value Low Register(ADCCVL) 9.3.7 Configuration Register (ADCCFG) ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power or long sample time. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1 ADR5 ADR4 ADR3 0 0 ...
Page 128
... Divide Ratio Table 9-7. Conversion Modes Mode Description 8-bit conversion (N=8) Reserved 10-bit conversion (N=10) Reserved MC9S08SG8 MCU Series Data Sheet, Rev MODE ADICLK Table Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ 8 Freescale Semiconductor 9-7. ...
Page 129
... ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table 9-8. Input Clock Select Selected Clock Source Bus clock Bus clock divided by 2 ...
Page 130
... ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled 130 Description ADPC13 ADPC12 ADPC11 Description MC9S08SG8 MCU Series Data Sheet, Rev ADPC10 ADPC9 ADPC8 Freescale Semiconductor ...
Page 131
... AD19 pin I/O control enabled 1 AD19 pin I/O control disabled 2 ADC Pin Control 18 — ADPC18 is used to control the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Description ADPC21 ...
Page 132
... Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC will not perform according to specifications. If the available clocks 132 Description MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 133
... In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08SG8 MCU Series Data Sheet, Rev. 6 ...
Page 134
... ADLSMP is used to select between short and long sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. The 134 MC9S08SG8 MCU Series Data Sheet, Rev After f ADCK Freescale Semiconductor ...
Page 135
... MHz, then the conversion time for a single conversion is: Conversion time = Number of bus cycles = 3.5 μ MHz = 28 cycles The ADCK frequency must be between f maximum to meet ADC specifications. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) frequency, precise sample time for continuous conversions ADCK ADICLK ...
Page 136
... If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. 136 NOTE MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 137
... Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) NOTE Conversions) is cleared when entering stop3 ...
Page 138
... Not used in this example Unimplemented or reserved, always reads zero Reserved for Freescale’s internal use; always write zero Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 139
... When available on a separate pin, both V as their corresponding MCU digital supply (V noise immunity and bypass capacitors placed as near as possible to the package. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ...
Page 140
... MC9S08SG8 MCU Series Data Sheet, Rev some devices. The low DDAD on some devices may be DDAD spec and the V potential (V DDAD must be connected to the same REFL . Setting the pin control register bits for and the input is equal to or REFL , the converter circuit converts it REFL Freescale Semiconductor REFH ...
Page 141
... I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: Place a 0.01 μF capacitor (C • improve noise issues but will affect sample rate based on the external analog source resistance). Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) lower than ...
Page 142
... Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the 142 LSB REFH REFL ). Note, if the last conversion is $3FE, then the LSB MC9S08SG8 MCU Series Data Sheet, Rev one-time error. LSB Eqn. 9-2 . LSB ). Note, if the first LSB LSB ) is used. LSB Freescale Semiconductor ) is ...
Page 143
... Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) and will increase with noise. This error may be LSB MC9S08SG8 MCU Series Data Sheet, Rev ...
Page 144
... Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 144 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 145
... When the internal reference is enabled in stop mode (IREFSTEN = 1), the voltage regulator must also be enabled in stop mode by setting the LVDE and LVDSE bits in the SPMSC1 register. Figure 10-1 shows the MC9S08SG8 block diagram with the ICS module highlighted. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 145 ...
Page 146
... REFH MC9S08SG8 MCU Series Data Sheet, Rev. 6 PTA3/PAI3/SCL/ADP3 PTA2/PAI2/SDA/ADP2/ACMPO PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ SEE NOTE 1, 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTB3/PIB3/MOSI/ADP7 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 PTB0/PIB0/RxD/ADP4 SEE NOTE 1, 2 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 /V , are double bonded to V and V respectively. SSA REFL DD SS Freescale Semiconductor ...
Page 147
... Control signals for a low power oscillator as the external reference clock are provided — HGO, RANGE, EREFS, ERCLKEN, EREFSTEN • FLL Engaged Internal mode is automatically selected out of reset 10.1.3 Block Diagram Figure 10-2 is the ICS block diagram. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 10 Internal Clock Source (S08ICSV2) 147 ...
Page 148
... FLL. 148 Block ERCLKEN EREFS EREFSTEN IRCLKEN IREFSTEN CLKS Internal LP Reference Clock DCOOUT 9 DCO TRIM 9 n RDIV_CLK Filter FLL Internal Clock Source Block l (FEI) (FEE) l (FBI) MC9S08SG8 MCU Series Data Sheet, Rev. 6 ICSERCLK ICSIRCLK BDIV ICSOUT n=0-3 ICSLCLK / 2 ICSFFCLK Freescale Semiconductor ...
Page 149
... ICS registers. Name 7 R ICSC1 CLKS W R ICSC2 BDIV W R ICSTRM ICSSC W Freescale Semiconductor l Low Power (FBILP) l (FBE) l Low Power (FBELP) Table 10-1. ICS Register Summary RDIV RANGE HGO LP TRIM 0 0 IREFST MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 10 Internal Clock Source (S08ICSV2) ...
Page 150
... Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before entering stop 0 Internal reference clock is disabled in stop 150 5 4 RDIV 0 0 Figure 10-3. ICS Control Register 1 (ICSC1) Description MC9S08SG8 MCU Series Data Sheet, Rev IREFS IRCLKEN IREFSTEN Freescale Semiconductor 0 0 ...
Page 151
... External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock EREFSTEN remains enabled when the ICS enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode before entering stop 0 External reference clock is disabled in stop Freescale Semiconductor 5 4 RANGE HGO 0 0 Figure 10-4 ...
Page 152
... CLKS bits due to internal synchronization between clock domains. 00 Output of FLL is selected. 01 FLL Bypassed, Internal reference clock is selected. 10 FLL Bypassed, External reference clock is selected. 11 Reserved. 152 TRIM Figure 10-5. ICS Trim Register (ICSTRM) Description IREFST Description MC9S08SG8 MCU Series Data Sheet, Rev CLKST OSCINIT FTRIM Freescale Semiconductor ...
Page 153
... The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the allowed movements between the states. 10.4.1.1 FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following conditions occur: Freescale Semiconductor Description IREFS=1 CLKS=00 FLL Engaged Internal (FEI) ...
Page 154
... In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal reference clock is enabled. 154 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 155
... After a change in the IREFS value the FLL will begin locking again after a few full cycles of the resulting divided reference frequency. The completion of the switch is shown by the IREFST bit. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 10 Internal Clock Source (S08ICSV2) ...
Page 156
... FLL and will only be used as ICSERCLK. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support (see the Overview chapter). 156 chapter). MC9S08SG8 MCU Series Data Sheet, Rev. 6 Device Freescale Semiconductor ...
Page 157
... BDIV=00 (divide by 1), RDIV ≥ 010 • BDIV=01 (divide by 2), RDIV ≥ 011 • BDIV=10 (divide by 4), RDIV ≥ 100 • BDIV=11 (divide by 8), RDIV ≥ 101 • Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 10 Internal Clock Source (S08ICSV2) 157 ...
Page 158
... Chapter 10 Internal Clock Source (S08ICSV2) 158 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 159
... IICPS in SOPT1 selects which general-purpose I/O ports are associated with IIC operation. IICPS in SOPT1 0 (default) 1 Figure 11-1 shows the MC9S08SG8 Series block diagram with the IIC module highlighted. Freescale Semiconductor NOTE Table 11-1. IIC Position Options Port Pin for SDA ...
Page 160
... REFH MC9S08SG8 MCU Series Data Sheet, Rev. 6 PTA3/PAI3/SCL/ADP3 PTA2/PAI2/SDA/ADP2/ACMPO PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ SEE NOTE 1, 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTB3/PIB3/MOSI/ADP7 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 PTB0/PIB0/RxD/ADP4 SEE NOTE 1, 2 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 /V , are double bonded to V and V respectively. SSA REFL DD SS Freescale Semiconductor ...
Page 161
... Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 11 Inter-Integrated Circuit (S08IICV2) 161 ...
Page 162
... This section consists of the IIC register descriptions in address order. 162 FREQ_REG ADDR_REG STATUS_REG Start Stop Arbitration Control SCL SDA Figure 11-2. IIC Functional Block Diagram MC9S08SG8 MCU Series Data Sheet, Rev. 6 Data Bus Interrupt DATA_MUX DATA_REG In/Out Data Shift Register Address Compare Freescale Semiconductor ...
Page 163
... IIC Frequency Divider Register (IICF MULT W Reset 0 0 Figure 11-4. IIC Frequency Divider Register (IICF) Freescale Semiconductor memory chapter of this document for the absolute address AD5 AD4 AD3 Figure 11-3 ...
Page 164
... MC9S08SG8 MCU Series Data Sheet, Rev. 6 × SDA hold value × SCL Start hold value × SCL Stop hold value SCL Start SCL Stop 3.000 5.500 4.000 5.250 4.000 5.250 4.250 5.125 4.750 5.125 Freescale Semiconductor Eqn. 11-1 Eqn. 11-2 Eqn. 11-3 Eqn. 11-4 ...
Page 165
... SCL SDA Hold (Start) (hex) Divider Value Value 104 21 17 128 112 17 1B 128 17 1C 144 25 1D 160 25 1E 192 33 1F 240 33 Freescale Semiconductor Table 11-5. IIC Divider and Hold Values SDA Hold ICR (Stop) (hex) Value 118 121 3F MC9S08SG8 MCU Series Data Sheet, Rev. 6 ...
Page 166
... Repeat start. Writing this bit generates a repeated start condition provided it is the current master. This RSTA bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration. 166 MST TX TXAK Figure 11-5. IIC Control Register (IICC1) Table 11-6. IICC1 Field Descriptions Description MC9S08SG8 MCU Series Data Sheet, Rev RSTA Freescale Semiconductor ...
Page 167
... Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after RXAK the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received Freescale Semiconductor BUSY 0 ARBL ...
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... IIC Control Register 2 (IICC2 GCAEN ADEXT W Reset Unimplemented or Reserved 168 DATA Figure 11-7. IIC Data I/O Register (IICD) Table 11-8. IICD Field Descriptions Description NOTE Figure 11-8. IIC Control Register (IICC2) MC9S08SG8 MCU Series Data Sheet, Rev AD10 AD9 AD8 Freescale Semiconductor ...
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... Stop signal The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Freescale Semiconductor Table 11-9. IICC2 Field Descriptions Description Figure MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11-9 ...
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... Bit Start Write Signal Figure 11-9. IIC Bus Transmission Signals MC9S08SG8 MCU Series Data Sheet, Rev. 6 lsb Data Byte No Ack Signal Bit lsb New Calling Address No Read/ Ack Write Bit Figure 11-9, a start signal is Figure 11-9). Freescale Semiconductor Stop Stop Signal ...
Page 171
... The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, Freescale Semiconductor 11-9. There is one clock pulse on SCL for each data bit, the msb being MC9S08SG8 MCU Series Data Sheet, Rev ...
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... SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 172 Delay Figure 11-10. IIC Clock Synchronization MC9S08SG8 MCU Series Data Sheet, Rev. 6 Figure 11-10). When all Start Counting High Period Freescale Semiconductor ...
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... After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. Freescale Semiconductor Table 11-10). When a 10-bit address follows a start condition, ...
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... ARBL bit in the status register is set. 174 Table 11-12 Table 11-12. Interrupt Summary Status TCF IAAS ARBL MC9S08SG8 MCU Series Data Sheet, Rev. 6 occur, provided the IICIE bit Flag Local Enable IICIF IICIE IICIF IICIE IICIF IICIE Freescale Semiconductor ...
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... A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing it. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 11 Inter-Integrated Circuit (S08IICV2) 175 ...
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... IIC operations. For slave operation, an Register Model AD[7:1] ICR MST TX TXAK RSTA BUSY ARBL 0 SRW DATA 0 0 AD10 0 Figure 11-11. IIC Module Quick Start MC9S08SG8 MCU Series Data Sheet, Rev IICIF RXAK AD9 AD8 Freescale Semiconductor ...
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... When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer Freescale Semiconductor Clear IICIF ...
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... Chapter 11 Inter-Integrated Circuit (S08IICV2) 178 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 179
... The external clock for the MTIM module, TCLK, is selected by setting CLKS = 1:1 or 1:0 in MTIMCLK, which selects the TCLK pin input. The TCLK input on PTA0 can be enabled as external clock inputs to both MTIM and TPM modules simultaneously. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 179 ...
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... REFH MC9S08SG8 MCU Series Data Sheet, Rev. 6 PTA3/PAI3/SCL/ADP3 PTA2/PAI2/SDA/ADP2/ACMPO PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ SEE NOTE 1, 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTB3/PIB3/MOSI/ADP7 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 PTB0/PIB0/RxD/ADP4 SEE NOTE 1, 2 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 /V , are double bonded to V and V respectively. SSA REFL DD SS Freescale Semiconductor ...
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... The MTIM suspends all counting until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as an MTIM reset did not occur (TRST written MOD written). MTIM Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 12 Modulo Timer (S08MTIMV1) 181 ...
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... CLKS TOF REG Table 12-1. Signal Properties Function External clock source input into MTIM MC9S08SG8 MCU Series Data Sheet, Rev. 6 12-2. 8-BIT COUNTER (MTIMCNT) 8-BIT COMPARATOR 8-BIT MODULO (MTIMMOD) Table 12-1. I/O I Pins and Connections chapter for Freescale Semiconductor TRST TSTP ...
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... Refer to the direct-page register summary in the assignments for all MTIM registers.This section refers to registers and control bits only by their names and relative address offsets. Some MCUs may have more than one MTIM, so register names include placeholder characters to identify which MTIM is being referenced. Freescale Semiconductor TOF ...
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... MTIM Counter Stop — When set, this read/write bit stops the MTIM counter at its current value. Counting resumes TSTP from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting. 0 MTIM counter is active. 1 MTIM counter is stopped. 3:0 Unused register bits, always read 0. 184 TSTP TRST Description MC9S08SG8 MCU Series Data Sheet, Rev Freescale Semiconductor ...
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... Encoding 4. MTIM clock source ÷ 16 0101 Encoding 5. MTIM clock source ÷ 32 0110 Encoding 6. MTIM clock source ÷ 64 0111 Encoding 7. MTIM clock source ÷ 128 1000 Encoding 8. MTIM clock source ÷ 256 All other encodings default to MTIM clock source ÷ 256. Freescale Semiconductor CLKS 0 ...
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... MTIM in free-running mode. Writing to MTIMMOD resets the COUNT to $00 and clears TOF. Reset sets the modulo to $00. 186 COUNT Figure 12-6. MTIM Counter Register Description MOD Figure 12-7. MTIM Modulo Register Modulo Register Field Descriptions MTIM Description MC9S08SG8 MCU Series Data Sheet, Rev Freescale Semiconductor ...
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... The MTIM allows for an optional interrupt to be generated whenever TOF is set. To enable the MTIM overflow interrupt, set the MTIM overflow interrupt enable bit (TOIE) in written while TOF = 1. Instead, TOF should be cleared first, then the TOIE can be set to 1. Freescale Semiconductor SC are used to select the desired clock source. If the counter is MTIM SC select the desired prescale value ...
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... The timer overflow flag, TOF, sets when the counter value changes from $AA to $00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1. 188 $A8 $A9 $AA $AA MC9S08SG8 MCU Series Data Sheet, Rev. 6 $00 $01 MOD register is set to $AA. MTIM Freescale Semiconductor ...
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... This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wake up from low power modes without the need of external components. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 189 ...
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... REFH MC9S08SG8 MCU Series Data Sheet, Rev. 6 PTA3/PAI3/SCL/ADP3 PTA2/PAI2/SDA/ADP2/ACMPO PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ SEE NOTE 1, 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTB3/PIB3/MOSI/ADP7 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 PTB0/PIB0/RxD/ADP4 SEE NOTE 1, 2 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 /V , are double bonded to V and V respectively. SSA REFL DD SS Freescale Semiconductor ...
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... The RTC suspends all counting during active background mode until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as the written and the RTCPS and RTCLKS bits are not altered. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 13 Real-Time Counter (S08RTCV1) ...
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... Figure 13-2. 8-Bit Modulo (RTCMOD) 8-Bit Comparator RTC 8-Bit Counter Clock (RTCCNT) Table 13-1. Register Summary RTC RTIF RTCLKS RTIE MC9S08SG8 MCU Series Data Sheet, Rev RTIF E R RTIE Write 1 to RTIF RTCPS RTCCNT RTCMOD Freescale Semiconductor RTC Interrupt Request 0 ...
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... See counters. Reset clears RTCPS. RTCLKS[ Off Off Freescale Semiconductor SC) RTC 5 4 RTCLKS RTIE 0 0 Table 13-2. RTCSC Field Descriptions Description Table 13-3. Changing the prescaler value clears the prescaler and RTCCNT Table 13-3. RTC Prescaler Divide-by values RTCPS ...
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... The RTC clock select bits (RTCLKS) select the desired clock source different value is written to RTCLKS, the prescaler and RTCCNT counters are reset to 0x00. 194 CNT) RTC RTCCNT Table 13-4. RTCCNT Field Descriptions Description MOD) RTC RTCMOD Table 13-5. RTCMOD Field Descriptions Description MC9S08SG8 MCU Series Data Sheet, Rev Freescale Semiconductor ...
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... RTC Operation Example This section shows an example of the RTC operation as the counter reaches a matching value from the modulo register. Freescale Semiconductor Table 13-6 Table 13-6. Prescaler Period 1-MHz External Clock 32-kHz Internal Clock (RTCLKS = 01) ...
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... Minutes = 0; Hours = 0; Days=0; /* Configure RTC to interrupt every 1 second from 1-kHz clock source */ RTCMOD.byte = 0x00; RTCSC.byte = 0x1F; /********************************************************************** Function Name : RTC_ISR Notes : Interrupt service routine for RTC module. **********************************************************************/ 196 0x53 0x54 0x55 MC9S08SG8 MCU Series Data Sheet, Rev. 6 0x55 0x00 0x01 Freescale Semiconductor ...
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... RTCSC.byte = RTCSC.byte | 0x80; /* RTC interrupts every 1 Second */ Seconds++; /* 60 seconds in a minute */ if (Seconds > 59){ Minutes++; Seconds = minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = hours in a day */ if (Hours > 23){ Days ++; Hours = Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 Chapter 13 Real-Time Counter (S08RTCV1) 197 ...
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... Chapter 13 Real-Time Counter (S08RTCV1) 198 MC9S08SG8 MCU Series Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction Figure 14-1 shows the MC9S08SG8 Series block diagram with the SCI module highlighted. Freescale Semiconductor MC9S08SG8 MCU Series Data Sheet, Rev. 6 199 ...
Page 200
... REFH MC9S08SG8 MCU Series Data Sheet, Rev. 6 PTA3/PAI3/SCL/ADP3 PTA2/PAI2/SDA/ADP2/ACMPO PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ SEE NOTE 1, 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTB3/PIB3/MOSI/ADP7 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 PTB0/PIB0/RxD/ADP4 SEE NOTE 1, 2 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 /V , are double bonded to V and V respectively. SSA REFL DD SS Freescale Semiconductor ...