S9S08SG8E2MTJ Freescale Semiconductor, S9S08SG8E2MTJ Datasheet - Page 204

• Manufacturer Part Number: S9S08SG8E2MTJ
• Description: MCU 2K FLASH 20-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG8E2MTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 14 Serial Communications Interface (S08SCIV4)
14.2
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
14.2.1
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIBDH to buffer the high half of the new value and then write
to SCIBDL. The working value in SCIBDH does not change until SCIBDL is written.
SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIC2 are written to 1).
204
RXEDGIE
SBR[12:8]
Reset
LBKDIE
Field
4:0
7
6
W
R
Register Definition
LBKDIE
SCI Baud Rate Registers (SCIBDH, SCIBDL)
LIN Break Detect Interrupt Enable (for LBKDIF)
0 Hardware interrupts from LBKDIF disabled (use polling).
1 Hardware interrupt requested when LBKDIF flag is 1.
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
0 Hardware interrupts from RXEDGIF disabled (use polling).
1 Hardware interrupt requested when RXEDGIF flag is 1.
Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the
modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to
reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in
Table
0
7
14-2.
= Unimplemented or Reserved
RXEDGIE
0
6
Figure 14-4. SCI Baud Rate Register (SCIBDH)
MC9S08SG8 MCU Series Data Sheet, Rev. 6
Table 14-1. SCIBDH Field Descriptions
0
0
5
Memory
SBR12
0
4
Description
chapter of this data sheet for the absolute address
SBR11
3
0
SBR10
0
2
Freescale Semiconductor
SBR9
0
1
SBR8
0
0