ST10F276Z5Q3TR STMicroelectronics, ST10F276Z5Q3TR Datasheet - Page 85
ST10F276Z5Q3TR
Manufacturer Part Number
ST10F276Z5Q3TR
Description
MCU 16BIT 832KBIT FLASH 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F276Z5T3.pdf
(239 pages)
Specifications of ST10F276Z5Q3TR
Core Processor
ST10
Core Size
16-Bit
Speed
64MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
68K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-QFP
Processor Series
ST10F27x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
68 KB
Interface Type
CAN, I2C
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
111
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
For Use With
497-6399 - KIT DEV STARTER ST10F276Z5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F276Z5Q3TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST10F276Z5
10
10.1
Table 47.
Pre-scaler factor
Input frequency
Resolution
Period maximum
f
CPU
= 40 MHz
General purpose timer unit
The GPT unit is a flexible multifunctional timer/counter structure which is used for time
related tasks such as event timing and counting, pulse width and duty cycle measurements,
pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized
into two separate modules GPT1 and GPT2. Each timer in each module may operate
independently in several different modes, or may be concatenated with another timer of the
same module.
GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for
one of four basic modes of operation: timer, gated timer, counter mode and incremental
interface mode.
In timer mode, the input clock for a timer is derived from the CPU clock, divided by a
programmable prescaler.
In counter mode, the timer is clocked in reference to external events.
Pulse width or duty cycle measurement is supported in gated timer mode where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input.
Table 47 and Table 48 list the timer input frequencies, resolution and periods for each pre-
scaler option at 40 MHz and 64 MHz CPU clock respectively.
In Incremental Interface mode, the GPT1 timers (T2, T3, T4) can be directly connected to
the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals so that the
contents of the respective timer Tx corresponds to the sensor position. The third position
sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow /
underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
high resolution of long duration measurements.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or
capture registers for timer T3.
GPT1 timer input frequencies, resolutions and periods at 40 MHz
13.1 ms
200 ns
5 MHz
000b
8
2.5 MHz
26.2 ms
400 ns
001b
16
1.25 MHz
52.4 ms
0.8 µs
010b
32
Timer Input Selection T2I / T3I / T4I
104.8 ms
625 kHz
1.6 µs
011b
64
312.5 kHz 156.25 kHz 78.125 kHz 39.1 kHz
209.7 ms
3.2 µs
100b
128
419.4 ms
6.4 µs
101b
256
General purpose timer unit
838.9 ms
12.8 µs
110b
512
25.6 µs
1.678 s
111b
1024
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