ST10F273M-4Q3 STMicroelectronics, ST10F273M-4Q3 Datasheet - Page 88
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ST10F273M-4Q3
Manufacturer Part Number
ST10F273M-4Q3
Description
MCU 16BIT 512K FLASH 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F273M-4TR3.pdf
(182 pages)
Specifications of ST10F273M-4Q3
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Processor Series
ST10F27x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F273M-4Q3
Manufacturer:
STMicroelectronics
Quantity:
10 000
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System reset
20.3
88/182
Figure 21. Asynchronous hardware RESET (EA = 0)
1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed).
2. 3 to 8 TCL depending on clock source selection.
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts: As already mentioned, if internal
Flash is used, the restarting occurs after the embedded Flash initialization routine is
completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are
driven to their inactive level. The ST10F273M starts program execution from memory
location 00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. The timings of asynchronous Hardware Reset sequence are
summarized in
Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (two periods of CPU clock): refer also to
details on minimum reset pulse duration. The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are
cancelled and the current internal access cycle if any is completed. External bus cycle is
aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
Longer than 500ns to take into account of Input Filter on RSTIN pin.
RPD
RSTIN
RSTF
(After Filter)
P0[15:13]
P0[12:2]
P0[1:0]
ALE
RST
Figure 20
not transparent
not transparent
and
≤ 500 ns
≥ 50 ns
Figure
21.
(1)
not transparent
transparent
transparent
system start-up configuration
Latching point of Port0 for
≤ 500 ns
≥ 50 ns
3..4 TCL
3..8 TCL
(2)
Section 20.1
not t.
not t.
not t.
8 TCL
ST10F273M
for
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