ST10F273M-4Q3 STMicroelectronics, ST10F273M-4Q3 Datasheet - Page 147
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ST10F273M-4Q3
Manufacturer Part Number
ST10F273M-4Q3
Description
MCU 16BIT 512K FLASH 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F273M-4TR3.pdf
(182 pages)
Specifications of ST10F273M-4Q3
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Processor Series
ST10F27x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F273M-4Q3
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST10F273M
24.8
24.8.1
24.8.2
AC characteristics
Test waveforms
Figure 44. Input/output waveforms
Figure 45. Float waveform
Definition of internal timing
The internal operation of the ST10F273M is controlled by the internal CPU clock f
edges of the CPU clock can trigger internal (for example pipeline) or external (for example
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate f
This influence must be regarded when calculating the timings for the ST10F273M.
The example for PLL operation shown in
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
For timing purposes a port pin is no longer floating when V
It begins to float when a 100mV change from the loaded V
V
LOAD
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at V
CPU
0.4V
2.4V
V
V
LOAD
LOAD
.
- 0.1V
+ 0.1V
2.0V
0.8V
Test Points
Figure 46
IH
Reference
Timing
Points
Min. for a logic ‘1’ and V
V
V
OL
OH
0.8V
refers to a PLL factor of 4.
2.0V
OH
LOAD
/ V
changes of ±100mV.
OL
level occurs (I
Electrical characteristics
IL
max for a logic ‘0’.
V
V
OH
OL
+ 0.1V
- 0.1V
OH
/ I
OL
CPU
= 20mA).
147/182
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