ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet - Page 60

• Manufacturer Part Number: ST10F272M-4T3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

General purpose timer unit
11.2
The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6)
and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived
from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down)
for each timer is programmable by software or may additionally be altered dynamically by an external
signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch
(T6OTL) of timer T6 which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The
overflow / underflow of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to
cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5
based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may
optionally be cleared after the capture procedure. This allows absolute time differences to be measured
or pulse multiplication to be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3
inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface mode.
Table 35
CPU clock.
Table 35.
60/176
Prescaler factor
Input frequency
Resolution
Period maximum
f
CPU
= 40 MHz
lists the timer input frequencies, resolution and periods for each prescaler option at 40 MHz
GPT2
GPT2 timer input frequencies, resolutions and periods at 40 MHz
6.55 ms
10 MHz
100 ns
000b
4
13.1 ms
200 ns
5 MHz
001b
8
2.5 MHz
26.2 ms
400 ns
010b
16
Timer input selection T5I/T6I
1.25 MHz
52.4 ms
0.8 µs
011b
32
104.8 ms
625 kHz
1.6 µs
100b
64
312.5 kHz
209.7 ms
3.2 µs
101b
128
156.25 kHz
419.4 ms
6.4 µs
110b
256
ST10F272M
78.125 kHz
838.9 ms
12.8 µs
111b
512