ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet - Page 22

• Manufacturer Part Number: ST10F272M-4T3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory organization
Note:
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After reset, the XRAM2 address range is 09’0000h - 09’3FFFh and is mirrored every
16 Kbyte boundary until 0F’FFFFh.
XRAM2 also represents the stand-by RAM, which can be maintained biased through
EA / V
memory, it cannot be used as system stack or as register banks. The XRAM is not provided
for single bit storage and therefore is not bit addressable.
SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function
register areas. SFRs are wordwide registers which are used to control and to monitor the
function of the different on-chip units.
CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 module access. The
CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit
0 of the XPERCON register. Accesses to the CAN module use demultiplexed addresses
and a 16-bit data bus (only word accesses are possible). Two wait states give an access
time of 100ns at 40 MHz CPU clock. No tri-state wait states are used.
CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. The
CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit
1 of the new XPERCON register. Accesses to the CAN module use demultiplexed
addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an
access time of 100ns at 40 MHz CPU clock. No tri-state wait states are used.
If one or the two CAN modules are used, port 4 cannot be programmed to output all eight
segment address lines. Thus, only four segment address lines can be used, reducing the
external memory space to 5 Mbytes (1 Mbyte per CS line).
RTC: Address range 00’ED00h - 00’EDFFh is reserved for the RTC Module access. The
RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON
register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz
CPU clock. No tristate waitstate is used.
PWM1: Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 module access.
The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the
XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16-
bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns
at 40 MHz CPU clock. No tristate waitstate is used. Only word access is possible.
ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 module access. The
ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON
register. Accesses to the ASC1 module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz
CPU clock. No tristate waitstate is used.
SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The
SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON
register. Accesses to the SSC1 module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz
CPU clock. No tristate waitstate is used.
I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I
enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register.
Accesses to the I
accesses are possible). Two waitstates give an access time of 100 ns at 40 MHz CPU clock.
No tristate waitstate is used.
STBY
pin when main supply VDD is turned off. As the XRAM appears like external
2
C module use demultiplexed addresses and a 16-bit data bus (only word
2
C module access. The I
ST10F272M
2
C is