STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 30
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STR912FAW47X6
Manufacturer Part Number
STR912FAW47X6
Description
MCU ARM9 2048KB FLASH 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STEVAL-IFW001V1.pdf
(102 pages)
Specifications of STR912FAW47X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR912x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
STR9
Device Core
ARM966E-S
Device Core Size
16/32Bit
Frequency (max)
96MHz
Total Internal Ram Size
96KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2/3.6V
Operating Supply Voltage (min)
1.65/1.77/2.5/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-9039
STR912FAW47X6
STR912FAW47X6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR912FAW47X6
Manufacturer:
ST
Quantity:
1 560
Company:
Part Number:
STR912FAW47X6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
STR912FAW47X6T
Manufacturer:
STMicroelectronics
Quantity:
10 000
Functional overview
3.16
3.17
30/102
Embedded trace module (ARM ETM9, v. r2p2)
The ETM9 interface provides greater visibility of instruction and data flow happening inside
the CPU core by streaming compressed data at a very high rate from the STR91xFA though
a small number of ETM9 pins to an external Trace Port Analyzer (TPA) device. The TPA is
connected to a host computer using USB, Ethernet, or other high-speed channel. Real-time
instruction flow and data activity can be recorded and later formatted and displayed on the
host computer running debugger software, and this software is typically integrated with the
debug software used for EmbeddedICE-RT functions such as single-step, breakpoints, etc.
Tracing may be triggered and filtered by many sources, such as instruction address
comparators, data watchpoints, context ID comparators, and counters. State sequencing of
up to three triggers is also provided. TPA hardware is commercially available and operates
with debugging software tools.
The ETM9 interface is nine pins total, four of which are data lines, and all pins can be used
for GPIO after tracing is no longer needed. The ETM9 interface is used in conjunction with
the JTAG interface for trace configuration. When tracing begins, the ETM9 engine
compresses the data by various means before broadcasting data at high speed to the TPA
over the four data lines. The most common ETM9 compression technique is to only output
address information when the CPU branches to a location that cannot be inferred from the
source code. This means the host computer must have a static image of the code being
executed for decompressing the ETM9 data. Because of this, self-modified code cannot be
traced.
Ethernet MAC interface with DMA
STR91xFA devices in 128-pin and 144-ball packages provide an IEEE-802.3-2002
compliant Media Access Controller (MAC) for Ethernet LAN communications through an
industry standard Medium Independent Interface (MII). The STR91xFA requires an external
Ethernet physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the STR91xFA MII port using as many as 18 signals
(see pins which have signal names MII_* in
The MAC corresponds to the OSI Data Link layer and the PHY corresponds to the OSI
Physical layer. The STR91xFA MAC is responsible for:
●
●
Data encapsulation, including frame assembly before transmission, and frame
parsing/error detection during and after reception.
Media access control, including initiation of frame transmission and recover from
transmission failure.
Doc ID 13495 Rev 6
Table
8).
STR91xFAxxx