STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 22
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STR912FAW47X6
Manufacturer Part Number
STR912FAW47X6
Description
MCU ARM9 2048KB FLASH 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STEVAL-IFW001V1.pdf
(102 pages)
Specifications of STR912FAW47X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR912x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
STR9
Device Core
ARM966E-S
Device Core Size
16/32Bit
Frequency (max)
96MHz
Total Internal Ram Size
96KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2/3.6V
Operating Supply Voltage (min)
1.65/1.77/2.5/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-9039
STR912FAW47X6
STR912FAW47X6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR912FAW47X6
Manufacturer:
ST
Quantity:
1 560
Company:
Part Number:
STR912FAW47X6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
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Functional overview
3.10.5
3.10.6
3.10.7
3.10.8
3.10.9
3.10.10
22/102
Flash memory interface clock (FMICLK)
The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at
power up. The clock can be optionally divided by 2. The FMICLK determines the bus
bandwidth between the ARM core and the Flash memory. Typically, codes in the Flash
memory can be fetched one word per FMICLK clock in burst mode. The maximum FMICLK
frequency is 96 MHz.
UART and SSP clock (BRCLK)
BRCLK is an internal clock derived from f
and to generate the Baud rate for the three on-chip UART peripherals. The frequency can
be optionally divided by 2.
External memory interface bus clock (BCLK)
The BCLK is an internal clock that controls the EMI bus. All EMI bus signals are
synchronized to the BCLK. The BCLK is derived from the HCLK and the frequency can be
configured to be the same or half that of the HCLK. Refer to
maximum BCLK frequency (f
an output pin.
USB interface clock
Special consideration regarding the USB interface: The clock to the USB interface must
operate at 48 MHz and comes from one of three sources, selected under firmware control:
●
●
●
Ethernet MAC clock
Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface
device requires it’s own 25 MHz clock source. This clock can come from one of two sources:
●
●
External RTC calibration clock
The RTC_CLK can be enabled as an output on the JRTCK pin. The RTC_CLK is used for
RTC oscillator calibration. The RTC_CLK is active in Sleep mode and can be used as a
system wake up control clock.
CCU master clock output of 48 MHz.
CCU master clock output of 96 MHz. An optional divided-by-two circuit is available to
produce 48 MHz for the USB while the CPU system runs at 96MHz.
STR91xFA pin P2.7. An external 48 MHz oscillator connected to pin P2.7 can directly
source the USB while the CCU master clock can run at some frequency other than 48
or 96 MHz.
A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xFA. In
this case, the STR91xFA must use a 25 MHz signal on its main oscillator input in order
to pass this 25 MHz clock back out to the PHY device through pin P5.2. The advantage
here is that an inexpensive 25 MHz crystal may be used to source a clock to both the
STR91xFA and the external PHY device.
An external 25 MHz oscillator connected directly to the external PHY interface device.
In this case, the STR91xFA can operate independent of 25 MHz.
BCLK
Doc ID 13495 Rev 6
). The BCLK clock is available on the LFBGA package as
MSTR
that is used to drive the two SSP peripherals
Table 17 on page 66
STR91xFAxxx
for the