STR911FAM44X6T STMicroelectronics, STR911FAM44X6T Datasheet - Page 28
![MCU ARM9 512KB FLASH 80LQFP](/photos/39/69/396970/tqfp-80_sml.jpg)
STR911FAM44X6T
Manufacturer Part Number
STR911FAM44X6T
Description
MCU ARM9 512KB FLASH 80LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STEVAL-IFW001V1.pdf
(102 pages)
Specifications of STR911FAM44X6T
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Processor Series
STR911x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
STR9-COMSTICK, STR910-EVAL, STR91X-SK/HIT, STR91X-SK/IAR, STR91X-SK/KEI, STR91X-SK/RAI, STR9-DK/RAIS, STR91X-DK/IAR, STX-PRO/RAIS, STR912-D/RAIS, STR79-RVDK/CPP, STR79-RVDKCPP/9, STR79-RVDK, STR79-RVDK/9, STR9-RVDK/BAS, STR79-RVDK/UPG
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES497-5067 - BOARD EVAL FOR STR910 FAMILY497-5066 - KIT STARTER KEIL FOR STR910497-5065 - KIT STARTER IAR KICKSTART STR912497-5064 - KIT STARTER FOR STR910 FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR911FAM44X6T
Manufacturer:
HITTITE
Quantity:
4 300
Company:
Part Number:
STR911FAM44X6T
Manufacturer:
STMicroelectronics
Quantity:
10 000
Functional overview
3.15.1
28/102
TAPs are daisy-chained, only one TAP will converse on the JTAG bus at any given time while
the other two TAPs are in BYPASS mode. The TAP positioning order within this JTAG chain
is the boundary scan TAP first, followed by the ARM debug TAP, followed by the Flash TAP.
All three TAP controllers are reset simultaneously by one of two methods:
●
●
This means that chip-level system resets from watchdog time-out or the assertion of
RESET_INn pin do not affect the operation of any JTAG TAP controller. Only global resets
effect the TAPs.
Figure 3.
In-system-programming
The JTAG interface is used to program or erase all memory areas of the STR91xFA device.
The pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid
instructions while the Flash memories are being programmed.
Note that the 32 bytes of OTP memory locations cannot be erased by any means once
programmed by JTAG ISP or the CPU.
JTRSTn
JRTCK
JTDO
JTMS
JTCK
JTDI
A chip-level global reset, caused only by a Power-On-Reset (POR) or a Low Voltage
Detect (LVD).
A reset command issued by the external JTAG test equipment. This can be the
assertion of the JTAG JTRSTn input pin on the STR91xFA or a JTAG reset command
shifted into the STR91xFA serially.
JTAG chaining inside the STR91xFA
TDO
MAIN FLASH
TDI
JTAG TAP CONTROLLER #1
JTAG TAP CONTROLLER #3
TMS
TMS
BOUNDARY SCAN
Doc ID 13495 Rev 6
TCK
TCK
SECONDARY FLASH
TRST
TRST
TDO
TDI
register length
Instruction
BURST FLASH
MEMORY DIE
is 8 bits
TDI
JTAG
JTAG TAP CONTROLLER #2
TRST
CPU DEBUG
TCK
TMS
TDO
ARM966ES DIE
5 bits for TAP #1
4 bits for TAP #2
register length:
Instruction
STR91xFAxxx
JTAG
STR91xx