Z86E4412VSG Zilog, Z86E4412VSG Datasheet - Page 50

• Manufacturer Part Number: Z86E4412VSG
• Description: IC MICROCONTROLLER 16K 44-PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E4412VSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: EBI/EMI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: Z86E4xx
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 3.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z86E4400ZDV, Z86E4400ZDP, Z86E4400ZDF, Z86E3400ZDV, Z86E3400ZDS, Z86E3400ZDP, Z86C4001ZDV
• Minimum Operating Temperature: 0 C
• For Use With: 309-1042 - ADAPTER 44-PLCC ZIF TO 44-PLCC309-1041 - ADAPTER 44-PLCC TO 44-PLCC309-1038 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1037 - ADAPTER 44-PLCC TO 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3981; Z86E4412VSG

Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Z8 CONTROL REGISTER DIAGRAMS
50
SMR (FH) 0B
D7
PCON (FH) 00H
*
** Default setting after RESET and STOP-Mode Recovery.
D7 D6 D5 D4 D3 D2 D1 D0
† Not used in conjunction with SMR2 Source
* Default Setting After Reset
† Must Be 1 for Z86E33/733/E34
Default setting after RESET.
Write Only Except Bit D7, Which is Read Only
D6 D5
Figure 37. STOP-Mode Recovery Register
Figure 36. Port Configuration Register
D4 D3 D2
D1 D0
Write Only
SCLK/TCLK Divide-by-16
0 OFF
1 ON
Stop Mode Recovery Source†
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag
0 POR*
1 Stop Recovery
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
1 10 P2 NOR 0-3
1 11 P2 NOR 0-7
Comparator Output Port 3
0 P34, P37 Standard*
1 P34, P37 Comparator Output
0 Port 1 Open-Drain
1 Port 1 Push-Pull Active*†
0 Port 0 Open-Drain
1 Port 0 Push-pull Active*
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 1 Low EMI
1 Port 1 Standard*†
0 Port 2 Low EMI
1 Port 2 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
Low EMI Oscillator
0 Low EMI
1 Standard*
**
P R E L I M I N A R Y
SMR2 (0F) DH
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
*
D7 D6 D5 D4 D3 D2 D1 D0
R240
Note: Not used in conjunction with SMR Source
Default setting after RESET
D7 D6 D5 D4 D3 D2 D1
Figure 39. STOP-Mode Recovery Register 2
Figure 38. Watch-Dog Timer Mode Register
Figure 40. Reserved
Write Only
Write Only
D0
WDT During HALT
0 OFF
1 ON
WDT During STOP
0 OFF
1 ON
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
WDT TAP
00
01
10
11
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
Reserved (Must be 0)
*
*
*
P25,P26,P27
Reserved (Must be 0)
INT RC OSC System Clock
80 ms
10 ms
20 ms
5 ms
*
DS97Z8X1500
2048 SCLK
128 SCLK
256 SCLK
512 SCLK
Zilog