Z86E4412VSG Zilog, Z86E4412VSG Datasheet - Page 38

• Manufacturer Part Number: Z86E4412VSG
• Description: IC MICROCONTROLLER 16K 44-PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E4412VSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: EBI/EMI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: Z86E4xx
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 3.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z86E4400ZDV, Z86E4400ZDP, Z86E4400ZDF, Z86E3400ZDV, Z86E3400ZDS, Z86E3400ZDP, Z86C4001ZDV
• Minimum Operating Temperature: 0 C
• For Use With: 309-1042 - ADAPTER 44-PLCC ZIF TO 44-PLCC309-1041 - ADAPTER 44-PLCC TO 44-PLCC309-1038 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1037 - ADAPTER 44-PLCC TO 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3981; Z86E4412VSG

FUNCTIONAL DESCRIPTION (Continued)
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
occurs in the V
register R254 is general-purpose on Z86E33/733/E34.
R254 and R255 are set to 00H after any reset or STOP-
Mode Recovery.
RAM Protect. The upper portion of the RAM's address
spaces 80H to EFH (excluding the control registers) can
be protected from reading and writing. This option can be
selected during the EPROM Programming Mode. After this
option is selected, the user can activate this feature from
the internal EPROM. D6 of the IMR control register (R251)
is used to turn off/on the RAM protect by loading a 0 or 1,
respectively. A "1" in D6 indicates RAM Protect enabled.
Stack. The
internal register file can be used for the stack. The 16-bit
Stack Pointer (R254-R255) is used for the external stack,
which can reside anywhere in the data memory for ROM-
less mode, but only from 4096/8192/16384 to 65535 in
ROM mode. An 8-bit Stack Pointer (R255) is used for the
internal stack on the Z8 that resides within the 236 gener-
al-purpose registers (R4-R239). SPH (R254) can be used
as a general-purpose register when using internal stack
only. R254 and R255 are set to 00H after any reset or
Stop- Mode Recovery.
38
Z86E43/743/E44
CC
voltage-specified operating range. The
external data memory or the
P R E L I M I N A R Y
Counter/Timers. There are two 8-bit programmable
counter/timers (T0 and T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler is driven by in-
ternal or external clock sources; however, the T0 prescaler
is driven by the internal clock only (Figure 27).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256), that has been loaded into the counter. When the
counter reaches the end of count, a timer interrupt request,
IRQ4 (T0) or IRQ5 (T1), is generated.
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching one (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
The counters, but not the prescalers, can be read at any
time without disturbing their value or count mode. The
clock source for T1 is user-definable and can be either the
internal microprocessor clock divided by four, or an exter-
nal signal input through Port 3. The Timer Mode register
configures the external timer input (P31) as an external
clock, a trigger input that can be retriggerable or non-retrig-
gerable, or as a gate input for the internal clock. Port 3 line
P36 serves as a timer output (T
or the internal clock can be output. The counter/timers can
be cascaded by connecting the T0 output to the input of
T1.
OUT
) through which T0, T1,
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