Z86E4412VSG Zilog, Z86E4412VSG Datasheet - Page 47

• Manufacturer Part Number: Z86E4412VSG
• Description: IC MICROCONTROLLER 16K 44-PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E4412VSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: EBI/EMI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: Z86E4xx
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 3.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z86E4400ZDV, Z86E4400ZDP, Z86E4400ZDF, Z86E3400ZDV, Z86E3400ZDS, Z86E3400ZDP, Z86C4001ZDV
• Minimum Operating Temperature: 0 C
• For Use With: 309-1042 - ADAPTER 44-PLCC ZIF TO 44-PLCC309-1041 - ADAPTER 44-PLCC TO 44-PLCC309-1038 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1037 - ADAPTER 44-PLCC TO 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3981; Z86E4412VSG

Zilog
Permanent WDT. When this feature is enabled, the WDT
is enabled after reset and will operate in Run and Halt
Mode. The control bits in the WDTMR do not affect the
WDT operation. If the clock source of the WDT is the inter-
nal RC oscillator, then the WDT will run in STOP mode. If
the clock source of the WDT is the XTAL1 pin, then the
WDT will not run in STOP mode.
Note: WDT time-out in STOP Mode will not reset
SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data
Registers, but will activate the Tpor delay.
WDTMR Register Accessibility. The WDTMR register is
accessible only during the first 60 internal system clock
DS97Z8X1500
WDTMR (F) 0F
*
D7 D6 D5 D4 D3 D2 D1 D0
Default setting after RESET
Figure 33. Watch-Dog Timer Mode Register
P R E L I M I N A R Y
Write Only
cycles from the execution of the first instruction after
Power-On Reset, Watch-Dog reset or a STOP-Mode
Recovery (Figures 33 and 34). After this point, the register
cannot be modified by any means, intentional or
otherwise. The WDTMR cannot be read and is located in
Bank F of the Expanded Register File at address location
0FH.
Clock Free WDT Reset. The WDT will enable the Z8 to
reset the I/O pins whenever the WDT times out, even with-
out a clock source running on the XTAL1 and XTAL2 pins.
WDTMR Bit D4 must be 0 for the clock Free WDT to work.
The I/O pins will default to their default settings
WDT During HALT
0 OFF
1 ON
WDT During STOP
0 OFF
1 ON
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
WDT TAP
00
01
10
11
*
*
*
INT RC OSC System Clock
80 ms
10 ms
20 ms
5 ms
*
2048 SCLK
CMOS Z8 OTP Microcontrollers
128 SCLK
256 SCLK
512 SCLK
Z86E33/733/E34/E43/743/E44
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