ST10R272LT1 STMicroelectronics, ST10R272LT1 Datasheet - Page 74

• Manufacturer Part Number: ST10R272LT1
• Description: MCU 16BIT ROMLESS LV 100-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R272LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R2x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 16 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ST10R272L - ELECTRICAL CHARACTERISTICS
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1
2
3
4
5
6
7
74/77
1
(Demux Bus)
The pending internal hold states are cancelled and the current internal access cycle (if
any) is completed.
RSTIN pulled low by internal device during internal reset sequence.
The reset condition may ends here if RSTIN pin is sampled high after t
Internal pullup devices are active on the PORT0 lines. Their input level is high if the
respective pin is left open, or is low if the respective pin is connected to an external pull-
down device by resistive high (pullup) after t
The ST10R272L starts execution here at address 00’0000h.
RSTOUT stays active until execution of the EINIT (End of Initialization) instruction.
Activation of the IO pins is controlled by software.
RSTOUT
RD, WR
Other IOs
PORT0
Internal
RSTIN
Signal
PORT1
Reset
ALE
Figure 28 External synchronous hardware reset (warm reset): Vpp high
6)
7)
t
70
t
77
t
711)
4)
t
722)
64
3)
.
t
74
t
t
73
75
t
76
t
78
72
.
5)