ST10R272LT1 STMicroelectronics, ST10R272LT1 Datasheet - Page 32

• Manufacturer Part Number: ST10R272LT1
• Description: MCU 16BIT ROMLESS LV 100-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R272LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R2x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 16 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ST10R272L - WATCHDOG TIMER
12
The Watchdog Timer is a fail-safe mechanism which limits the malfunction time of the
controller. The Watchdog Timer is always enabled after device reset and can only be disabled
in the time interval until the EINIT (end of initialization) instruction has been executed. In this
way, the chip’s start-up procedure is always monitored. The software must be designed to
service the Watchdog Timer before it overflows. If, due to hardware or software related
failures, the software fails to maintain the Watchdog Timer, it will overflow generating an
internal hardware reset and pulling the RSTOUT pin low to reset external hardware
components.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by
128. The high byte of the Watchdog Timer register can be set to a pre-specified reload value
(stored in WDTREL) in order to allow further variation of the monitored time interval. Each
time it is serviced by the application software, the high byte of the Watchdog Timer is
reloaded. The table below shows the watchdog time range which for a 50MHz CPU clock
rounded to 3 significant figures.
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1
SSPCKS Value
011
100
101
110
111
Reload value
in WDTREL
FF
00
H
H
WATCHDOG TIMER
Table 11 Synchronous baud rate and SSPCKS reload values
SSP clock = CPU clock divided by 16
SSP clock = CPU clock divided by 32
SSP clock = CPU clock divided by 64
SSP clock = CPU clock divided by 128
SSP clock = CPU clock divided by 256
Table 12 Watchdog timer range
Prescaler for f
2 (WDTIN = ‘0’)
10.24 µs
2.62 ms
CPU
128 (WDTIN = ‘1’)
655 µs
168 ms
Synchronous baud rate
3.13 MBit/s
1.56 MBit/s
781 KBit/s
391 KBit/s
195 KBit/s