ST72F561K9T3 STMicroelectronics, ST72F561K9T3 Datasheet - Page 261

• Manufacturer Part Number: ST72F561K9T3
• Description: IC MCU 8BIT 60K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561K9T3

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

IMPORTANT NOTES (Cont’d)
Figure 154.LINSCI Interrupt Routine
16.1.6 TIMD set simultaneously with OC
interrupt
If the 16-bit timer is disabled at the same time the
output compare event occurs then the output com-
pare flag gets locked and cannot be cleared be-
fore the timer is enabled again.
Impact on the application: If output compare in-
terrupt is enabled, then the output compare flag
cannot be cleared in the timer interrupt routine.
Consequently the interrupt service routine is called
repeatedly and the application get stuck which
causes the watchdog reset if enabled by the appli-
cation.
Workaround: Disable the timer interrupt before
disabling the timer. Again while enabling, first ena-
ble the timer, then the timer interrupts.
Perform the following to disable the timer:
– TACR1 or TBCR1 = 0x00h; // Disable the com-
– TACSR | or TBCSR | = 0x40; // Disable the timer
– Perform the following to enable the timer again:
– TACSR & or TBCSR &= ~0x40; // Enable the tim-
– TACR1 or TBCR1 = 0x40; // Enable the compare
pare interrupt
er
interrupt
@interrupt void LINSCI_IT ( void ) /* LINSCI interrupt routine */
{
}
/* clear flags */
SCISR_buffer = SCISR;
SCIDR_buffer = SCIDR;
if ( SCISR_buffer & LHE )/* header error ? */
{
}
if (!LHLR)/* header time-out? */
{
}
{
}
if ( !(SCICR2 & RWU) )/* active mode ? */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
_asm("rim");/* enable interrupts */
_asm("sim");/* disable interrupts */
16.1.7 CAN FIFO Corruption
The beCAN FIFO gets corrupted when a message
is received and simultaneously a message is re-
leased while FMP = 2. For details and a descrip-
tion of the workaround refer to
page
16.2 FLASH/FASTROM DEVICES ONLY
16.2.1 LINSCI Wrong Break Duration
SCI mode
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- 20 bits instead of 10 bits if M = 0
- 22 bits instead of 11 bits if M = 1
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Occurrence
The occurrence of the problem is random and pro-
portional to the baud rate. With a transmit frequen-
cy
of
187.
19200
Example using Cosmic compiler syntax
baud
(f
CPU
Section 10.9.7.1 on
= 8 MHz
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