ST72F561K9TA STMicroelectronics, ST72F561K9TA Datasheet - Page 26

• Manufacturer Part Number: ST72F561K9TA
• Description: IC MCU 8BIT 60K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561K9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a V
V
ply. The V
age is lower than the V
rising voltage in order to avoid parasitic detection
(hysteresis).
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte.
6.4.2.1 Monitoring the V
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
V
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
Figure 16. Using the AVD to Monitor V
26/265
IT+(AVD)
IT-(AVD)
AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
V
V
V
V
IT+(AVD)
IT+(LVD)
IT-(LVD)
IT-(AVD)
threshold (AVDF bit toggles).
reference value and the V
IT-(AVD)
V
DD
reference value for falling volt-
0
IT+(AVD)
DD
Main Supply
reference value for
1
DD
INTERRUPT PROCESS
IT-(AVD)
IT+(AVD)
main sup-
V
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
DD
hyst
RESET VALUE
and
or
down safely before the LVD resets the microcon-
troller. See
The interrupt on the rising edge is used to inform
the application that the V
If the voltage rise time t
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
ated when V
If t
– If the AVD interrupt is enabled before the
– If the AVD interrupt is enabled after the V
V
terrupts will be received: The first when the
AVDIE bit is set and the second when the thresh-
old is reached.
threshold is reached, then only one AVD inter-
rupt occurs.
rv
IT+(AVD)
is greater than 256 or 4096 cycles then:
threshold is reached, then two AVD in-
Figure
IT+(AVD)
t
1
16.
rv
VOLTAGE RISE TIME
is reached.
rv
DD
is less than 256 or 4096
warning state is over.
INTERRUPT PROCESS
0
IT+(AVD)