STM32F102C6T6ATR STMicroelectronics, STM32F102C6T6ATR Datasheet - Page 50
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STM32F102C6T6ATR
Manufacturer Part Number
STM32F102C6T6ATR
Description
MCU 32BIT ARM 32K FLASH 48-LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F102C6T6A.pdf
(69 pages)
Specifications of STM32F102C6T6ATR
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
48MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
STM32F102x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
37
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
For Use With
497-10030 - STARTER KIT FOR STM32497-6438 - BOARD EVALUTION FOR STM32 512K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F102C6T6ATR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Electrical characteristics
5.3.13
50/69
Figure 20. I/O AC characteristics definition
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under ambient temperature and V
Table
Table 36.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 21. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
V
V
V
V
V
NF(NRST)
IH(NRST)
Symbol
IL(NRST)
F(NRST)
to the series resistance must be minimum
Table
hys(NRST)
R
8.
PU
36. Otherwise the reset will not be taken into account by the device.
(1)
(1)
(1)
PU
(1)
External
reset circuit
NRST pin characteristics
(see
EXT ERNAL
OUTPUT
ON 50pF
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
Maximum frequency is achieved if (t r + t f ) 2/3)T and if the duty cycle is (45-55%)
Table
(1)
0.1 µF
33).
Parameter
t r(I O)out
NRST
Doc ID 15057 Rev 3
(2)
(~10% order)
10%
V DD
50%
when loaded by 50pF
R PU
90%
(2)
.
DD
Conditions
supply voltage conditions summarized in
V
T
IN
10%
Table 36
V
50%
SS
Filter
90%
t r(I O)out
STM32F102x4, STM32F102x6
STM32F10xxx
–0.5
are derived from tests
IL(NRST)
Min
300
30
Internal Reset
2
max level specified in
Typ
200
40
V
DD
ai14132c
Max
100
0.8
50
+0.5
ai14131
Unit
mV
k
ns
ns
V