ST7FLIT19BF1M3 STMicroelectronics, ST7FLIT19BF1M3 Datasheet - Page 66
![IC MCU 8BIT 4K FLASH 20-SOIC](/photos/6/56/65691/497-20-soic__7_5mm_width__series_sml.jpg)
ST7FLIT19BF1M3
Manufacturer Part Number
ST7FLIT19BF1M3
Description
IC MCU 8BIT 4K FLASH 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLIT15BY1M6.pdf
(159 pages)
Specifications of ST7FLIT19BF1M3
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLIT1x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLIT1B-D/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-6232 - BOARD EVAL ST7LITE1B,STP5NK60Z497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLIT19BF1M3
Manufacturer:
ST
Quantity:
20 000
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
– At the second input capture on the falling edge of
Figure 46. Long Range Input Capture Timing Diagram
66/159
1
the pulse, we assume that the values in the reg-
isters are as follows:
LTICR = LT2
ATICRH = ATH2
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2
f
TB Counter1
CNTR1
LTIC
LTICR
ATICRH
ATICRL
OSC/32
_ _ _
F9h
00h
00h
0h
00h
LT1
ATH1 & ATL1
F9h
00h
Now pulse width P between first capture and sec-
ond capture will be:
P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + dec-
imal ((FFF * N) + N + ATICR2 - ATICR1 – 1) * 1ms
where N = No of overflows of 12-bit CNTR1.
ATH1
LT1
ATL1
_ _ _
_ _ _
ATICR = ATICRH[3:0] & ATICRL[7:0]
_ _ _
_ _ _
LT2
_ _ _
ATH2 & ATL2
ATH2
ATL2
LT2
_ _ _