ST7FLIT19BF1M3 STMicroelectronics, ST7FLIT19BF1M3 Datasheet - Page 42
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ST7FLIT19BF1M3
Manufacturer Part Number
ST7FLIT19BF1M3
Description
IC MCU 8BIT 4K FLASH 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLIT15BY1M6.pdf
(159 pages)
Specifications of ST7FLIT19BF1M3
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLIT1x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLIT1B-D/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-6232 - BOARD EVAL ST7LITE1B,STP5NK60Z497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLIT19BF1M3
Manufacturer:
ST
Quantity:
20 000
ST7LITE1xB
POWER SAVING MODES (Cont’d)
9.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when ACTIVE-HALT is disabled
(see
when the AWUEN bit in the AWUCSR register is
cleared.
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 37) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see
ure
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im-
mediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
tion 15.1 on page 149
Figure 25. HALT Timing Overview
42/159
1
[Active Halt disabled]
INSTRUCTION
RUN
26).
section 9.5 on page 43
HALT
HALT
256 OR 4096 CPU
CYCLE DELAY
INTERRUPT
for more details).
RESET
OR
for more details) and
VECTOR
FETCH
RUN
sec-
Fig-
Figure 26. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after a delay of t
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
(Active Halt disabled)
N
WATCHDOG
WDGHALT
Table 5 Interrupt Mapping
RESET
1
INTERRUPT
Y
1)
ENABLE
3)
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
CPU
I BIT
CPU
I BIT
CPU
I BIT
STARTUP
N
CYCLE
RESET
for more details.
Y
WATCHDOG
(see
DELAY
DISABLE
Figure
2)
OFF
OFF
OFF
OFF
ON
ON
X
5)
ON
ON
ON
X
0
4)
4)
13).