ST7FLITE39F2M3TR STMicroelectronics, ST7FLITE39F2M3TR Datasheet - Page 44

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ST7FLITE39F2M3TR

Manufacturer Part Number
ST7FLITE39F2M3TR
Description
IC MCU 8BIT 8K FLASH 20SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITE39F2M3TR

Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE39F2M3TR
Manufacturer:
ST
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Part Number:
ST7FLITE39F2M3TR
Manufacturer:
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Quantity:
20 000
ST7LITE3xF2
POWER SAVING MODES (Cont’d)
Similarities with Halt mode
The following AWUFH mode behaviour is the
same as normal Halt mode:
– The MCU can exit AWUFH mode by means of
– When entering AWUFH mode, the I bit in the CC
Figure 29. AWUF Halt Timing Diagram
44/173
1
AWUFH interrupt
f
any interrupt with exit from Halt capability or a re-
set (see
register is forced to 0 to enable interrupts. There-
fore, if an interrupt is pending, the MCU wakes
up immediately.
f
AWU_RC
CPU
Section 9.4 HALT
RUN MODE
MODE).
HALT MODE
t
AWU
– In AWUFH mode, the main oscillator is turned off
– The compatibility of Watchdog operation with
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
None of the peripherals are clocked except those
which get their clock supply from another clock
generator (such as an external or auxiliary oscil-
lator like the AWU oscillator).
AWUFH mode is configured by the WDGHALT
option bit in the option byte. Depending on this
setting, the HALT instruction when executed
while the Watchdog system is enabled, can gen-
erate a Watchdog RESET.
256 OR 4096 t
CPU
RUN MODE
Clear
by software

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